ADVANCED MICRO DEVICES, INC.
Patent Owner
Back to search resultsStats
- 8 5,244 total patents issued
- 1,806 Total Apps Published
- May 07, 2013 most recent publication
Details
- 5,244 Issued Patents
- 568 Issued in last 3 years
- 649 Published in last 3 years
- 68,512 Total Citation Count
- Dec 15, 1977 Earliest Filing
- 1,422 Expired/Abandoned/Withdrawn Patents
Technologies
Intl Class
Technology
# of Patents
Rank
Top Patents (by citation)
Patent #
Title
Filing Date
Issue Date
Intl Class
Cited #
6,272,377
Cardiac rhythm management system with arrhythmia prediction and prevention
Oct 01, 99
Aug 07, 01
[A61B]
273
5,859,964
System and method for performing real time data acquisition, process modeling and fault detection of wafer fabrication processes
Oct 25, 96
Jan 12, 99
[G06F]
209
5,926,690
Run-to-run control process for controlling critical dimensions
May 28, 97
Jul 20, 99
[G01R, H01L]
187
6,368,954
Method of copper interconnect formation using atomic layer copper deposition
Jul 28, 00
Apr 09, 02
[H01L]
152
6,573,172
Methods for improving carrier mobility of PMOS and NMOS devices
Sep 16, 02
Jun 03, 03
[H01L]
145
5,944,841
Microprocessor with built-in instruction tracing capability
Apr 15, 97
Aug 31, 99
[G06F]
144
5,761,064
Defect management system for productivity and yield improvement
Oct 06, 95
Jun 02, 98
[G06F]
137
6,087,269
Method of making an interconnect using a tungsten hard mask
Apr 20, 98
Jul 11, 00
[H01L]
135
Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2013/0105,975
SEMICONDUCTOR CHIP DEVICE WITH THERMAL INTERFACE MATERIAL FRAME
Oct 26, 11
May 02, 13
[H01L]
2013/0103,908
PREVENTING UNINTENDED LOSS OF TRANSACTIONAL DATA IN HARDWARE TRANSACTIONAL MEMORY SYSTEMS
Dec 13, 12
Apr 25, 13
[G06F]
2013/0095,648
TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS
Nov 20, 12
Apr 18, 13
[H01L]
2013/0097,385
DUAL-GRANULARITY STATE TRACKING FOR DIRECTORY-BASED CACHE COHERENCE
Oct 18, 11
Apr 18, 13
[G06F]
2013/0083,048
INTEGRATED CIRCUIT WITH ACTIVE MEMORY AND PASSIVE VARIABLE RESISTIVE MEMORY WITH SHARED MEMORY CONTROL LOGIC AND METHOD OF MAKING SAME
Sep 28, 12
Apr 04, 13
[G06T, G11C, H01L]
2013/0083,591
Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets
Sep 29, 11
Apr 04, 13
[G11C]
2013/0086,357
STAGGERED READ OPERATIONS FOR MULTIPLE OPERAND INSTRUCTIONS
Sep 29, 11
Apr 04, 13
[G06F]
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
8,436,647
Pipeline power gating for gates with multiple destinations
Dec 22, 11
May 07, 13
[G06F, H03K]
8,431,466
Method of forming finned semiconductor devices with trench isolation
Jul 05, 11
Apr 30, 13
[H01L]
8,432,207
Method and apparatus for correcting the duty cycle of a high speed clock
Dec 30, 11
Apr 30, 13
[H03K]
8,423,320
Method and system for quantitative inline material characterization in semiconductor production processes based on structural measurements and related models
Apr 03, 09
Apr 16, 13
[G01B]
8,423,846
Integrated circuit with memory built-in self test (MBIST) circuitry having enhanced features and methods
Sep 16, 10
Apr 16, 13
[G01R]
Top Inventors for This Owner
Inventor Name
Address
Patent #