ALTERA CORPORATION
Patent Owner
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- 0 4,058 US PATENTS IN FORCE
- 26 US APPLICATIONS PENDING
- Mar 20, 2018 most recent publication
Details
- 4,058 Issued Patents
- 10 Issued in last 3 years
- 0 Published in last 3 years
- 67,553 Total Citation Count
- May 03, 1984 Earliest Filing
- 536 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
Technologies
Intl Class
Technology
MATTERS
Rank in Class
Intl Class
Technology
MATTERS
Rank in Class
- No Technologies to Display
Top Patents (by citation)
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Patent #
Title
Filing Date
Issue Date
Intl Class
CITATIONS
5260611
Programmable logic array having local and long distance conductors
May 08, 92
Nov 09, 93
[H03K]
441
5260610
Programmable logic element interconnections for programmable logic array integrated circuits
Sep 03, 91
Nov 09, 93
[H03K]
414
5537057
Programmable logic array device with grouped logic regions and three types of conductors
Feb 14, 95
Jul 16, 96
[H03K]
277
5371422
Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
Mar 29, 93
Dec 06, 94
[H03K]
266
6215326
Programmable logic device architecture with super-regions having logic regions and a memory region
Mar 10, 99
Apr 10, 01
[H03K]
259
5121006
Registered logic macrocell with product term allocation and adjacent product term stealing
Apr 22, 91
Jun 09, 92
[H03K]
249
6538470
Devices and methods with programmable logic and digital signal processing regions
Sep 18, 01
Mar 25, 03
[H03K]
245
5258668
Programmable logic array integrated circuits with cascade connections between logic modules
May 08, 92
Nov 02, 93
[H03K]
241
- No Patents to Display
Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2018/0039,724
Method and Apparatus for Verifying Structural Correctness in Retimed Circuits
Oct 22, 17
Feb 08, 18
[G06F]
2018/0032,857
Method and Apparatus for Performing Different Types of Convolution Operations with the Same Processing Elements
Dec 01, 16
Feb 01, 18
[G06N]
2018/0006,653
INTEGRATED CIRCUITS WITH HYBRID FIXED/CONFIGURABLE CLOCK NETWORKS
Jun 29, 16
Jan 04, 18
[G06F, H03K]
2018/0006,664
METHODS AND APPARATUS FOR PERFORMING REED-SOLOMON ENCODING BY LAGRANGIAN POLYNOMIAL FITTING
Jun 29, 16
Jan 04, 18
[H03M]
2017/0337,318
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices
Jul 30, 17
Nov 23, 17
[G06F]
2017/0328,951
EMBEDDED BUILT-IN SELF-TEST (BIST) CIRCUITRY FOR DIGITAL SIGNAL PROCESSOR (DSP) VALIDATION
May 13, 16
Nov 16, 17
[G01R, G11C]
2017/0322,813
PIPELINED CASCADED DIGITAL SIGNAL PROCESSING STRUCTURES AND METHODS
Jul 28, 17
Nov 09, 17
[G06F]
2017/0316,120
Method and Apparatus for Implementing a System-Level Design Tool for Design Planning and Architecture Exploration
Jul 14, 17
Nov 02, 17
[G06F]
- No Publications to Display
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
9922150
Method and apparatus for satisfying operating conditions in a system design using an electronic design automation tool
Nov 11, 14
Mar 20, 18
[G06F]
9922156
Method and apparatus for automatic hierarchical design partitioning
Jul 31, 14
Mar 20, 18
[G06F]
9917513
Integrated circuit voltage regulator with adaptive current bleeder circuit
Dec 03, 14
Mar 13, 18
[G05F, H02M]
9911477
Memory controller architecture with improved memory scheduling efficiency
Apr 18, 14
Mar 06, 18
[G11C, G06F]
9912337
Systems and methods for configuring an SOPC without a need to use an external memory
Jan 06, 17
Mar 06, 18
[G06F, H03K]
9912369
Methods and apparatus for adaptively maintaining a communications link during idle mode
Dec 08, 15
Mar 06, 18
[H04L, H04B]
- No Patents to Display
Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
2017/0237,433
Circuits and Methods For Impedance Calibration
Abandoned
May 01, 17
Aug 17, 17
[H03H, H03K]
2016/0225,437
METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN MEMORY CIRCUITRY BY CONTROLLING PRECHARGE DURATION
Abandoned
Feb 04, 15
Aug 04, 16
[G11C]
2015/0263,082
INDUCTOR STRUCTURES WITH IMPROVED QUALITY FACTOR
Abandoned
Mar 11, 14
Sep 17, 15
[H01L]
2015/0200,156
MODULE HAVING MIRROR-SYMMETRIC TERMINALS AND METHODS OF FORMING THE SAME
Abandoned
Jan 13, 14
Jul 16, 15
[H01L]
2015/0012,903
NON-INTRUSIVE MONITORING AND CONTROL OF INTEGRATED CIRCUITS
Abandoned
May 19, 14
Jan 08, 15
[G06F]
2014/0374,877
Integrated Circuits With On-Die Decoupling Capacitors
Abandoned
Jun 21, 13
Dec 25, 14
[H01L]
2014/0355,665
Adaptive Video Reference Frame Compression with Control Elements
Abandoned
May 31, 13
Dec 04, 14
[H04N]
2014/0264,783
APPARATUS FOR ELECTRONIC ASSEMBLY WITH IMPROVED INTERCONNECT AND ASSOCIATED METHODS
Abandoned
Mar 13, 13
Sep 18, 14
[H01L]
2014/0255,028
SUB-RATE MAPPING FOR LOWEST-ORDER OPTICAL DATA UNIT
Abandoned
Mar 08, 13
Sep 11, 14
[H04B]
- No Patents to Display
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