ALTERA CORPORATION

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Technologies

Intl Class Technology # of Patents Rank
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 985 38
 
 
H03K PULSE TECHNIQUE 697 3
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 249 93
 
 
G11C STATIC STORES 237 28
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 94 13
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 91 48
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 89 85
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 71 40
 
 
G02B OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS 61 101
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 49 18
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Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,260,611 Programmable logic array having local and long distance conductors May 08, 92 Nov 09, 93 [H03K] 409
5,260,610 Programmable logic element interconnections for programmable logic array integrated circuits Sep 03, 91 Nov 09, 93 [H03K] 389
5,689,195 Programmable logic array integrated circuit devices May 17, 95 Nov 18, 97 [H03K] 268
5,550,782 Programmable logic array integrated circuits May 18, 94 Aug 27, 96 [G11C] 268
5,121,006 Registered logic macrocell with product term allocation and adjacent product term stealing Apr 22, 91 Jun 09, 92 [H03K] 233
5,537,057 Programmable logic array device with grouped logic regions and three types of conductors Feb 14, 95 Jul 16, 96 [H03K] 230
5,258,668 Programmable logic array integrated circuits with cascade connections between logic modules May 08, 92 Nov 02, 93 [H03K] 226
5,371,422 Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements Mar 29, 93 Dec 06, 94 [H03K] 205
5,350,954 Macrocell with flexible product term allocation Mar 29, 93 Sep 27, 94 [H03K] 198
5,815,726 Coarse-grained look-up table architecture Jun 07, 95 Sep 29, 98 [H03K] 189
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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0111,253 TIME DIVISION MULTIPLEXED MULTIPORT MEMORY Oct 28, 11 May 02, 13 [G06F]
2013/0093,482 CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES Dec 04, 12 Apr 18, 13 [H03L]
2013/0069,230 ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS Sep 07, 12 Mar 21, 13 [H01L]
2013/0069,247 APPARATUS FOR STACKED ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS Sep 16, 11 Mar 21, 13 [H01L]
2013/0071,969 ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS Sep 07, 12 Mar 21, 13 [H01L]
2013/0073,763 MEMORY ARBITRATION CIRCUITRY Sep 16, 11 Mar 21, 13 [G06F]
2013/0061,247 PROCESSOR TO MESSAGE-BASED NETWORK INTERFACE USING SPECULATIVE TECHNIQUES Feb 09, 12 Mar 07, 13 [G06F]
2013/0043,536 BUFFERED FINFET DEVICE Aug 19, 11 Feb 21, 13 [H01L]
2013/0043,902 APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS Aug 19, 11 Feb 21, 13 [H03K]
2013/0019,082 Manifold Array Processor Sep 14, 12 Jan 17, 13 [G06F]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,436,646 Reconfigurable logic block with user RAM Jul 01, 11 May 07, 13 [H03K]
8,437,200 Zeroization verification of integrated circuit Feb 07, 11 May 07, 13 [G11C]
8,438,521 Methods and apparatus for implementing application specific processors May 30, 08 May 07, 13 [G06F]
8,432,724 Memory elements with soft error upset immunity Apr 02, 10 Apr 30, 13 [G11C]
8,433,322 Processor for a base station control unit Jun 13, 11 Apr 30, 13 [H04Q]
8,433,744 Programmable multiply accumulate (MAC) circuit Sep 22, 08 Apr 30, 13 [G06F]
8,433,930 One-time programmable memories for key storage Sep 17, 10 Apr 30, 13 [H04L]
8,433,958 Bit error rate checker receiving serial data signal from an eye viewer Sep 17, 10 Apr 30, 13 [G06F]
8,433,976 Row column interleavers and deinterleavers with efficient memory usage Apr 27, 10 Apr 30, 13 [G11C, G06F, H03M]
8,434,039 Method for incorporating pattern dependent effects in circuit simulations Mar 28, 11 Apr 30, 13 [G06F]
8,434,044 Specifying placement and routing constraints for security and redundancy Dec 14, 10 Apr 30, 13 [G06F]
8,427,213 Robust time borrowing pulse latches Jan 10, 12 Apr 23, 13 [H03K]
8,427,347 Dynamic data compression and decompression Mar 30, 11 Apr 23, 13 [H03M]
8,428,179 Apparatus and method for crest factor reduction Jul 15, 10 Apr 23, 13 [H04L]
8,429,491 Methods and apparatus for error checking code decomposition Nov 20, 09 Apr 23, 13 [H03M]
8,429,591 Methods and apparatus for single testing stimulus Mar 07, 11 Apr 23, 13 [G06F]
8,423,932 Block emulation techniques in integrated circuits Jun 04, 10 Apr 16, 13 [G06F]

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Top Inventors for This Owner

Inventor Name Address Patent #
Sung Chiakang
Milpitas, US
176
Shumarayev Sergey
San Leandro, US
162
Huang Joseph
Morgan Hill, US
158
Cliff Richard G
Milpitas, US
148
Wong Wilson
San Francisco, US
141
Lee Andy L
San Jose, US
121
Lewis David
Toronto, CA
117
Pedersen Bruce B
San Jose, US
106
Patel Rakesh H
Cupertino, US
104
Langhammer Martin
Poole Dorset
95
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