AURIGA INNOVATIONS, INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 222176
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 4443
 
  
 
C08L COMPOSITIONS OF MACROMOLECULAR COMPOUNDS 2114
 
  
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 2154
 
  
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM1156
 
  
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 1103
 
  
 
H01G CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE 165

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Recent Publications

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9673089 Interconnect structure with enhanced reliabilityOct 31, 14Jun 06, 17[H01L]
9515140 Patterned strained semiconductor substrate and deviceJan 16, 08Dec 06, 16[H01L]
9502288 Method of forming an interconnect structureMar 15, 12Nov 22, 16[H01L, H05K]
9362229 Semiconductor devices with enhanced electromigration performanceOct 16, 14Jun 07, 16[H01L]
9337315 FinFET spacer formation by oriented implantationJan 17, 14May 10, 16[H01L]
9318375 Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep viasAug 13, 09Apr 19, 16[H01L]
9318578 FinFET spacer formation by oriented implantationSep 27, 12Apr 19, 16[H01L]
9105509 Ball grid array and card skew matching optimizationDec 17, 10Aug 11, 15[H01L, G06F]
9059021 FinFET deviceMar 03, 14Jun 16, 15[H01L]
9059290 FinFET device formationJun 05, 14Jun 16, 15[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2014/0167,109 CONTINUOUS METAL SEMICONDUCTOR ALLOY VIA FOR INTERCONNECTSAbandonedFeb 24, 14Jun 19, 14[H01L]
2013/0234,260 INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWNAbandonedApr 26, 13Sep 12, 13[H01L]
2013/0012,025 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHSAbandonedSep 14, 12Jan 10, 13[H01L]
2013/0001,789 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAMEAbandonedSep 14, 12Jan 03, 13[H01L]
7800184 Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contactExpiredJan 09, 06Sep 21, 10[H01L]
7777339 Semiconductor chips with reduced stress from underfill at edge of chipExpiredJul 30, 07Aug 17, 10[H01L]
7718496 devices using high-K metal gate stacksExpiredOct 30, 07May 18, 10[H01L]
7714452 Structure and method for producing multiple size interconnectionsExpiredAug 30, 07May 11, 10[H01L]
7709967 Shapes-based migration of aluminum designs to copper damasceneExpiredAug 13, 07May 04, 10[H01L]
7655557 CMOS silicide metal gate integrationExpiredJun 24, 08Feb 02, 10[H01L]
7498250 Shapes-based migration of aluminum designs to copper damasceneExpiredAug 13, 07Mar 03, 09[H01L]
7479683 Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectricsExpiredOct 01, 04Jan 20, 09[H01L]
7459785 Electrical interconnection structure formationExpiredNov 16, 07Dec 02, 08[H01L]
2008/0258,198 STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOSAbandonedJul 02, 08Oct 23, 08[H01L]
2008/0029,841 STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING DIELECTRIC CHAMBERAbandonedOct 10, 07Feb 07, 08[H01L]
2007/0287,256 Contact scheme for FINFET structures with multiple FINsAbandonedJun 07, 06Dec 13, 07[H01L]
7306853 Patternable low dielectric constant materials and their use in ULSI interconnectionExpiredDec 21, 05Dec 11, 07[C08L]
7300867 Dual damascene interconnect structures having different materials for line and via conductorsExpiredJul 05, 05Nov 27, 07[H01L]
7288475 Sacrificial inorganic polymer intermetal dielectric damascene wire and via linerExpiredNov 13, 06Oct 30, 07[H01L]
7273777 Formation of fully silicided (FUSI) gate using a dual silicide processExpiredAug 02, 05Sep 25, 07[H01L]

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