CHARTERED SEMICONDUCTOR MANUFACTURING LTD.

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Intl Class Technology # of Patents Rank
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 65644
 
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 1868
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 12288
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 1042
 
 
 
G03C PHOTOSENSITIVE MATERIALS FOR PHOTOGRAPHIC PURPOSES 942
 
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 846
 
 
 
B08B CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL 742
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7121
 
 
 
B05D PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL 563
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 466

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,989,978 Shallow trench isolation of MOSFETS with reduced corner parasitic currentsJul 16, 98Nov 23, 99[H01L]184
5,856,225 Creation of a self-aligned, ion implanted channel region, after source and drain formationNov 24, 97Jan 05, 99[H01L]148
6,376,353 Aluminum and copper bimetallic bond pad scheme for copper damascene interconnectsJul 03, 00Apr 23, 02[H01L]107
5,728,621 Method for shallow trench isolationApr 28, 97Mar 17, 98[H01L]107
6,436,824 Low dielectric constant materials for copper damasceneJul 02, 99Aug 20, 02[H01L]101
5,595,919 Method of making self-aligned halo process for reducing junction capacitanceFeb 20, 96Jan 21, 97[H01L]99
6,040,243 Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusionSep 20, 99Mar 21, 00[H01L]96
6,884,712 Method of manufacturing semiconductor local interconnect and contactFeb 07, 03Apr 26, 05[H01L]91
5,744,376 Method of manufacturing copper interconnect with top barrier layerApr 08, 96Apr 28, 98[H01L]88
6,492,726 Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnectionSep 22, 00Dec 10, 02[H01L]86

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2012/0119,293 HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYERDec 21, 11May 17, 12[H01L]
2012/0074,519 CRACK STOP STRUCTURE ENHANCEMENT OF THE INTEGRATED CIRCUIT SEAL RINGSep 26, 11Mar 29, 12[H01L]
2011/0278,645 STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMINGJul 26, 11Nov 17, 11[H01L]
2011/0237,039 Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain RegionsMar 23, 10Sep 29, 11[H01L]
2011/0227,136 SPACER PROTECTION AND ELECTRICAL CONNECTION FOR ARRAY DEVICEMar 22, 10Sep 22, 11[H01L]
2011/0169,096 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERSJan 14, 10Jul 14, 11[H01L]
2011/0006,349 FIELD EFFECT TRANSISTOR HAVING CHANNEL SILICON GERMANIUMJul 13, 09Jan 13, 11[H01L]
2010/0320,503 STRAINED CHANNEL TRANSISTOR AND METHOD OF FABRICATION THEREOFAug 09, 10Dec 23, 10[H01L]
2010/0289,088 THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYERMay 14, 09Nov 18, 10[H01L]
2010/0283,101 PATTERNING NANOCRYSTAL LAYERSMay 07, 09Nov 11, 10[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,338,245 Integrated circuit system employing stress-engineered spacersMar 14, 08Dec 25, 12[H01L]
8,236,646 Non-volatile memory manufacturing method using STI trench implantationNov 06, 03Aug 07, 12[H01L]
8,236,699 Contact patterning method with transition etch feedbackFeb 07, 11Aug 07, 12[H01L]
8,211,761 Semiconductor system using germanium condensationAug 16, 06Jul 03, 12[H01L]
8,198,194 Methods of forming p-channel field effect transistors having SiGe source/drain regionsMar 23, 10Jun 12, 12[H01L]
8,158,513 Integrated circuit system employing backside energy source for electrical contact formationOct 08, 08Apr 17, 12[H01L]
8,138,053 Method of forming source and drain of field-effect-transistor and structure thereofJun 15, 07Mar 20, 12[H01L]
8,138,055 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the sameAug 04, 10Mar 20, 12[H01L]
8,115,276 Integrated circuit system employing back end of line via techniquesJun 03, 08Feb 14, 12[H01L]
8,105,955 Integrated circuit system with carbon and non-carbon siliconAug 15, 06Jan 31, 12[H01L]

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Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
Chan Lap
Singapore, SG
152
Zhou Mei Sheng
Singapore, SG
102
Chooi Simon
Singapor, SG
96
Zheng Jia Zhen
Singapore, SG
91
Quek Elgin
Singapore, SG
63
Pan Yang
Singapore, SG
60
Gupta Subhash
Singapore, SG
57
Pradeep Yelehanka Ramachandramurthy
Singapore, SG
56
Hsia Liang Choo
Singapore, SG
55
See Alex
Singapore, SG
54