CHIPPAC, INC.
Patent Owner
Stats
- 67 total patents issued
- 84 Total Apps Published
- Mar 27, 2012 most recent publication
Details
- 67 Issued Patents
- 10 Issued in last 3 years
- 0 Published in last 3 years
- 1,236 Total Citation Count
- Mar 09, 2001 Earliest Filing
- 0 Expired/Abandoned/Withdrawn Patents
Technologies
Intl Class
Technology
# of Patents
Rank
Top Patents (by citation)
Patent #
Title
Filing Date
Issue Date
Intl Class
Cited #
6,838,761 Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shieldAug 02, 03Jan 04, 05[H01L]91
6,906,416 Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) packageOct 08, 03Jun 14, 05[H01L]69
6,933,598 Semiconductor stacked multi-package module having inverted second package and electrically shielded first packageOct 08, 03Aug 23, 05[H01L]64
6,972,481 Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packagesAug 02, 03Dec 06, 05[H01L]63
7,064,426 Semiconductor multi-package module having wire bond interconnect between stacked packagesAug 02, 03Jun 20, 06[H01L]55
7,045,887 Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) packageOct 08, 03May 16, 06[H01L]49
7,053,476 Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packagesAug 02, 03May 30, 06[H01L]46
7,049,691 Semiconductor multi-package module having inverted second package and including additional die or stacked package on second packageOct 08, 03May 23, 06[H01L]46
7,034,387 Semiconductor multipackage module including processor and memory package assembliesJul 14, 03Apr 25, 06[H01L]45
7,053,477 Semiconductor multi-package module having inverted bump chip carrier second packageOct 08, 03May 30, 06[H01L]42
Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2007/0155,053 Semiconductor Multi-Package Module Having Package Stacked Over Ball Grid Array Package and Having Wire Bond Interconnect Between Stacked PackagesMar 09, 07Jul 05, 07[H01L]
2007/0114,648 Semiconductor Stacked Multi-Package Module Having Inverted Second PackageJan 23, 07May 24, 07[H01L]
2007/0117,267 Semiconductor Multi-Package Module Having Inverted Land Grid Array (LGA) Package Stacked Over Ball Grid Array (BGA) PackageJan 23, 07May 24, 07[H01L]
2007/0111,388 Semiconductor Multi-Package Module Having Inverted Second Package Stacked Over Die-Up Flip-Chip Ball Grid Array (BGA) PackageJan 12, 07May 17, 07[H01L]
2007/0018,296 Stacked Semiconductor Package having Adhesive/Spacer Structure and InsulationSep 28, 06Jan 25, 07[H01L]
2007/0013,060 Stacked Semiconductor Package having Adhesive/Spacer Structure and InsulationSep 21, 06Jan 18, 07[H01L]
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
8,143,100 Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packagesAug 31, 07Mar 27, 12[H01L]
8,030,134 Stacked semiconductor package having adhesive/spacer structure and insulationSep 28, 06Oct 04, 11[H01L]
7,935,572 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packagesApr 26, 10May 03, 11[H01L]
7,880,313 Semiconductor flip chip package having substantially non-collapsible spacerNov 17, 05Feb 01, 11[H01L]
7,749,807 Method of fabricating a semiconductor multipackage module including a processor and memory package assembliesDec 10, 07Jul 06, 10[H01L]
Top Inventors for This Owner
Inventor Name
Address
# of Patent/Pub