CYPRESS SEMICONDUCTOR CORPORATION

Patent Owner

Watch Compare Add to Portfolio 5Status Updates

Stats

Details

Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 65867
 
 
 
G11C STATIC STORES 55222
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 395167
 
 
 
H03K PULSE TECHNIQUE 13138
 
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 10327
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7586
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 4040
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 3575
 
 
 
H04B TRANSMISSION 35167
 
 
 
G09G ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION 31121

Top Patents (by citation)

Upgrade to the Premium Level to View Top Patents for this Owner. Learn More

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0286,344 Dynamically Reconfigurable Analog Routing and Multiplexing Architecture on a System on a ChipMar 20, 17Oct 05, 17[G06F]
2017/0287,366 SYSTEMS AND METHODS FOR DOWNLOADING CODE AND DATA INTO A SECURE NON-VOLATILE MEMORYApr 13, 17Oct 05, 17[H04L, G06F, G09C]
2017/0277,241 LOW-POWER TOUCH BUTTON SENSING SYSTEMApr 18, 17Sep 28, 17[G01R, G06F, H03K]
2017/0278,853 INTEGRATION OF A MEMORY TRANSISTOR INTO HIGH-K, METAL GATE CMOS PROCESS FLOWMar 15, 17Sep 28, 17[H01L]
2017/0262,035 TYPE-C CONNECTOR SUBSYSTEMMar 21, 17Sep 14, 17[G06F]
2017/0262,094 Sensor Array with Edge PatternMar 01, 17Sep 14, 17[G06F]
2017/0262,097 Single Layer Sensor PatternApr 21, 17Sep 14, 17[G06F]
2017/0262,685 Fingerprint Sensor-Compatible Overlay MaterialMar 29, 17Sep 14, 17[G06K]
2017/0263,309 10-Transistor Non-Volatile Static Random-Access Memory Using A Single Non-Volatile Memory Element And Method Of Operation ThereofApr 13, 17Sep 14, 17[G11C]
2017/0263,459 MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE AND METHOD OF MANUFACTURING THEREOFMay 26, 17Sep 14, 17[H01L]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9811135 Low-power type-C receiver with high idle noise and DC-level rejectionDec 21, 15Nov 07, 17[G06F, H02J]
9813232 Device and method for resisting non-invasive attacksMar 17, 15Nov 07, 17[H04L, G06F]
9804858 System for re-enumeration of USB 3.0 compatible peripheral devicesSep 27, 16Oct 31, 17[G06F]
9804859 Re-enumeration of USB 3.0 compatible devicesSep 19, 14Oct 31, 17[G06F]
9798909 Integrated circuit to convert no-wire signals to one-wire signalsSep 30, 16Oct 24, 17[H04L, H04Q, H04B, G06K]
9792049 Memory subsystem with wrapped-to-continuous readFeb 24, 14Oct 17, 17[G06F]
9793125 SONOS stack with split nitride memory layerAug 11, 15Oct 17, 17[G11C, H01L]
9793284 Method of ONO stack formationNov 16, 15Oct 17, 17[H01L]
9793883 Valley detection circuit and drive circuitSep 26, 16Oct 17, 17[G01R, H03K, H02M]
9785613 Acoustic processing unit interface for determining senone scores using a greater clock frequency than that corresponding to received audioJun 06, 12Oct 10, 17[G06F, G10L]

View all patents..

Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2015/0255,480 Method to Improve Charge Trap Flash Memory Top Oxide QualityABANMay 06, 14Sep 10, 15[H01L]
2015/0200,295 Drain Extended MOS Transistors With Split ChannelABANSep 24, 14Jul 16, 15[H01L]
2015/0187,960 Radical Oxidation Process For Fabricating A Nonvolatile Charge Trap Memory DeviceABANJan 26, 15Jul 02, 15[H01L]
2015/0155,162 Reduction of Charging Induced Damage in Photolithography Wet ProcessABANDec 03, 13Jun 04, 15[H01L]
2015/0097,224 BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITSABANOct 08, 13Apr 09, 15[H01L]
2015/0035,044 Method to Improve Charge Trap Flash Memory Core Cell Performance and ReliabilityABANSep 15, 14Feb 05, 15[H01L]
2015/0003,182 MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATEABANSep 15, 14Jan 01, 15[G11C]
2014/0327,553 ZERO POWER METERING CIRCUITS, SYSTEMS AND METHODSABANSep 26, 13Nov 06, 14[G01D]
2014/0293,717 MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATEABANJan 14, 14Oct 02, 14[G11C]
2014/0233,339 APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBSABANFeb 18, 13Aug 21, 14[G11C]
2014/0225,177 FLASH MEMORY CELLS HAVING TRENCHED STORAGE ELEMENTSABANApr 16, 14Aug 14, 14[H01L]
2014/0215,111 VARIABLE READ LATENCY ON A SERIAL MEMORY BUSABANMar 28, 14Jul 31, 14[G06F]
2014/0191,308 SELF-ALIGNED DOUBLE PATTERNING FOR MEMORY AND OTHER MICROELECTRONIC DEVICESABANMar 11, 14Jul 10, 14[H01L]
2014/0195,233 Distributed Speech Recognition SystemABANJan 08, 13Jul 10, 14[G10L]
2014/0167,136 Charge Trapping Device with Improved Select Gate to Memory Gate IsoloationABANDec 14, 12Jun 19, 14[H01L]
2014/0167,141 Charge Trapping Split Gate Embedded Flash Memory and Associated MethodsABANDec 14, 12Jun 19, 14[H01L]
2014/0167,142 Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory CellsABANDec 14, 12Jun 19, 14[H01L]
2014/0167,220 THREE DIMENSIONAL CAPACITORABANDec 14, 12Jun 19, 14[H01L]
2014/0151,887 Memory Device Interconnects and Method of ManufactureABANDec 10, 13Jun 05, 14[H01L]
2014/0148,009 Forming a Substantially Uniform Wing Height Among Elements in a Charge Trap Semiconductor DeviceABANNov 26, 12May 29, 14[H01L]

View all patents..

Top Inventors for This Owner

Upgrade to the Premium Level to View Top Inventors for this Owner. Learn More

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to -1 comparisons!

We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.