CYPRESS SEMICONDUCTOR CORPORATION

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 65273
 
 
 
G11C STATIC STORES 54222
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 394174
 
 
 
H03K PULSE TECHNIQUE 12642
 
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 10126
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7690
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 3943
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 3873
 
 
 
H04B TRANSMISSION 36174
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 31254

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2018/0068,735 Method to Reduce Program Disturbs in Non-Volatile Memory CellsNov 08, 17Mar 08, 18[G11C]
2018/0053,657 SONOS Stack With Split Nitride Memory LayerJul 28, 17Feb 22, 18[G11C, H01L]
2018/0024,945 Context-based protection systemJul 18, 17Jan 25, 18[G06F]
2018/0025,199 NON-FINGER OBJECT REJECTION FOR FINGERPRINT SENSORSSep 22, 17Jan 25, 18[G06K]
2018/0025,202 Anti-Spoofing Protection for Fingerprint ControllersMar 22, 17Jan 25, 18[G06K]
2018/0011,718 RE-ENUMERATION OF USB 3.0 COMPATIBLE DEVICESJul 20, 17Jan 11, 18[G06F]
2018/0012,055 FINGERPRINT SENSOR PATTERNJun 22, 17Jan 11, 18[G06K]
2018/0006,132 VARIED SILICON RICHNESS SILICON NITRIDE FORMATIONAug 30, 17Jan 04, 18[H01L]
2017/0371,451 PROVIDING A BASELINE CAPACITANCE FOR A CAPACITANCE SENSING CHANNELJul 26, 17Dec 28, 17[G06F]
2017/0371,824 BUS SHARING SCHEMEJul 11, 17Dec 28, 17[G06F]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9922833 Charge trapping split gate embedded flash memory and associated methodsDec 16, 15Mar 20, 18[H01L]
9922988 Embedded SONOS based memory cellsMar 06, 17Mar 20, 18[H01L]
9923572 Delta modulator receive channel for capacitance measurement circuitsMar 31, 16Mar 20, 18[G01R, H03F, H03M]
9917166 Memory first process flow and deviceJun 13, 16Mar 13, 18[H01L]
9917211 Flash memory cells having trenched storage elementsApr 16, 14Mar 13, 18[H01L]
9910077 Detect and differentiate touches from different size conductive objects on a capacitive buttonJul 26, 17Mar 06, 18[G01R, G06F]
9910544 Uniformity correction method for low cost and non-rectangular touch sensor matricesSep 20, 17Mar 06, 18[G06F]
9910729 Restoring ECC syndrome in non-volatile memory devicesJul 14, 15Mar 06, 18[G11C, G06F]
9910823 Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetchMay 09, 12Mar 06, 18[G06F]
9911613 Method of fabricating a charge-trapping gate stack using a CMOS process flowOct 26, 16Mar 06, 18[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2015/0255,480 Method to Improve Charge Trap Flash Memory Top Oxide QualityAbandonedMay 06, 14Sep 10, 15[H01L]
2015/0206,893 DAMASCENE OXYGEN BARRIER AND HYDROGEN BARRIER FOR FERROELECTRIC RANDOM-ACCESS MEMORYAbandonedSep 23, 14Jul 23, 15[H01L]
2015/0200,295 Drain Extended MOS Transistors With Split ChannelAbandonedSep 24, 14Jul 16, 15[H01L]
2015/0194,499 VARIED SILICON RICHNESS SILICON NITRIDE FORMATIONAbandonedMar 23, 15Jul 09, 15[H01L]
2015/0194,537 MULTI-LAYER INTER-GATE DIELECTRIC STRUCTUREAbandonedJan 07, 14Jul 09, 15[H01L]
2015/0171,104 COMPLEMENTARY SONOS INTEGRATION INTO CMOS FLOWAbandonedJun 16, 14Jun 18, 15[H01L]
2015/0162,226 Forming Charge Trap Separation in a Flash Memory Semiconductor DeviceAbandonedFeb 19, 15Jun 11, 15[H01L]
2015/0155,162 Reduction of Charging Induced Damage in Photolithography Wet ProcessAbandonedDec 03, 13Jun 04, 15[H01L]
2015/0097,224 BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITSAbandonedOct 08, 13Apr 09, 15[H01L]
2015/0091,138 Die Seal Layout for VFTL Dual Damascene in a Semiconductor DeviceAbandonedDec 10, 14Apr 02, 15[H01L]
2015/0035,044 Method to Improve Charge Trap Flash Memory Core Cell Performance and ReliabilityAbandonedSep 15, 14Feb 05, 15[H01L]
2015/0003,182 MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATEAbandonedSep 15, 14Jan 01, 15[G11C]
2014/0332,876 HIGH VOLTAGE GATE FORMATIONAbandonedJul 24, 14Nov 13, 14[H01L]
2014/0327,553 ZERO POWER METERING CIRCUITS, SYSTEMS AND METHODSAbandonedSep 26, 13Nov 06, 14[G01D]
2014/0293,717 MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATEAbandonedJan 14, 14Oct 02, 14[G11C]
2014/0233,339 APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBSAbandonedFeb 18, 13Aug 21, 14[G11C]
2014/0210,012 Manufacturing of FET Devices Having Lightly Doped Drain and Source RegionsAbandonedJan 31, 13Jul 31, 14[H01L]
2014/0215,111 VARIABLE READ LATENCY ON A SERIAL MEMORY BUSAbandonedMar 28, 14Jul 31, 14[G06F]
2014/0195,233 Distributed Speech Recognition SystemAbandonedJan 08, 13Jul 10, 14[G10L]
2014/0167,136 Charge Trapping Device with Improved Select Gate to Memory Gate IsoloationAbandonedDec 14, 12Jun 19, 14[H01L]

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