ELPIDA MEMORY, INC.

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Technologies

Intl Class Technology # of Patents Rank
 
 
G11C STATIC STORES 868 9
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 737 41
 
 
H03K PULSE TECHNIQUE 117 34
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 77 231
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 49 77
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 45 43
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 44 33
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 23 79
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 18 66
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 15 44
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Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,726,083 Process of fabricating dynamic random access memory device having storage capacitor low in contact resistance and small in leakage current through tantalum oxide film Nov 28, 95 Mar 10, 98 [H01L] 221
5,341,341 Dynamic random access memory device having addressing section and/or data transferring path arranged in pipeline architecture Mar 23, 93 Aug 23, 94 [G11C] 175
6,081,456 Bit line control circuit for a memory array using 2-bit non-volatile memory cells Feb 04, 99 Jun 27, 00 [G11C] 159
6,181,597 EEPROM array using 2-bit non-volatile memory cells with serial read operations Feb 04, 99 Jan 30, 01 [G11C] 147
6,256,231 EEPROM array using 2-bit non-volatile memory cells and method of implementing same Feb 04, 99 Jul 03, 01 [G11C] 137
6,147,904 Redundancy method and structure for 2-bit non-volatile memory cells Feb 04, 99 Nov 14, 00 [G11C] 136
6,044,022 Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays Feb 26, 99 Mar 28, 00 [G11C] 135
6,157,570 Program/erase endurance of EEPROM memory cells Feb 04, 99 Dec 05, 00 [G11C] 132
6,381,190 Semiconductor memory device in which use of cache can be selected May 11, 00 Apr 30, 02 [G06F] 127
6,330,205 Virtual channel synchronous dynamic random access memory Dec 21, 00 Dec 11, 01 [G11C] 125
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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0126,963 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME Dec 14, 12 May 23, 13 [H01L]
2013/0127,048 DEVICE Nov 07, 12 May 23, 13 [H01L]
2013/0132,797 CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE Jan 14, 13 May 23, 13 [G06F]
2013/0119,512 Top Electrode Templating for DRAM Capacitor Oct 31, 12 May 16, 13 [H01L]
2013/0119,513 Adsorption Site Blocking Method for Co-Doping ALD Films Dec 04, 12 May 16, 13 [H01L]
2013/0119,514 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Dec 12, 12 May 16, 13 [H01L]
2013/0119,546 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD May 03, 12 May 16, 13 [H01L]
2013/0121,091 SYSTEM WITH CONTROLLER AND MEMORY Jan 08, 13 May 16, 13 [G11C]
2013/0121,092 SEMICONDUCTOR DEVICE INCLUDING PLURAL SEMICONDUCTOR CHIPS STACKED TO ONE ANOTHER Nov 07, 12 May 16, 13 [G11C]
2013/0122,678 ADSORPTION SITE BLOCKING METHOD FOR CO-DOPING ALD FILMS Nov 11, 11 May 16, 13 [H01L]
2013/0122,681 TOP ELECTRODE TEMPLATING FOR DRAM CAPACITOR Nov 11, 11 May 16, 13 [H01L]
2013/0122,682 ANNEAL TO MINIMIZE LEAKAGE CURRENT IN DRAM CAPACITOR Nov 14, 11 May 16, 13 [H01L]
2013/0122,683 BLOCKING LAYERS FOR LEAKAGE CURRENT REDUCTION IN DRAM DEVICES Jan 10, 13 May 16, 13 [H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,446,214 Semiconductor device and method of controlling the same Oct 28, 11 May 21, 13 [G05F]
8,440,537 Adsorption site blocking method for co-doping ALD films Nov 11, 11 May 14, 13 [H01L]
8,441,126 Semiconductor device May 12, 11 May 14, 13 [H01L]
8,441,135 Semiconductor device Jul 31, 12 May 14, 13 [H01L]
8,441,832 Semiconductor device and test method thereof Jul 22, 11 May 14, 13 [G11C]
8,441,840 Semiconductor device and data processing system Jan 13, 11 May 14, 13 [G11C]
8,441,879 Semiconductor memory device requiring refresh operation Jan 22, 10 May 14, 13 [G11C]
8,435,854 Top electrode templating for DRAM capacitor Nov 11, 11 May 07, 13 [H01L]
8,436,409 Semiconductor device Aug 31, 11 May 07, 13 [H01L]
8,436,655 Voltage level shift circuit and semiconductor device Jun 03, 11 May 07, 13 [H03K]

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Top Inventors for This Owner

Inventor Name Address Patent #
Kajigaya Kazuhiko
Tokyo, JP
218
Fujisawa Hiroki
Tokyo, JP
182
Ikeda Hiroaki
Tokyo, JP
84
Ishikawa Toru
Tokyo, JP
79
Nishio Yoji
Tokyo, JP
79
Katagiri Mitsuaki
Tokyo, JP
78
Takemura Riichiro
Tokyo, JP
78
Sekiguchi Tomonori
Tokyo, JP
76
Asano Isamu
Tokyo, JP
75
Noda Hiromasa
Tokyo, JP
64
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