FASL LLC

5,852,576 High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gateOct 06, 97Dec 22, 98[G11C]13

5,995,415 Simultaneous operation flash memory device with a flexible bank partition architectureSep 23, 98Nov 30, 99[G11C]12

7,038,948 Read approach for multi-level virtual ground memorySep 22, 04May 02, 06[G11C]7

6,808,992 Method and system for tailoring core and periphery cells in a nonvolatile memoryMay 15, 02Oct 26, 04[H01L]7

7,251,158 Erase algorithm for multi-level bit flash memoryJun 10, 04Jul 31, 07[G11C]6

7,307,338 Three dimensional polymer memory cell systemsJul 26, 04Dec 11, 07[H01L]5

7,163,860 Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory deviceMay 06, 03Jan 16, 07[H01L]5

Recent Publications

2006/0120,151 Method of determining voltage compensation for flash memory devicesJan 27, 06Jun 08, 06[G11C]

2006/0062,054 READ APPROACH FOR MULTI-LEVEL VIRTUAL GROUND MEMORYSep 22, 04Mar 23, 06[G11C]

2005/0276,120 Erase algorithm for multi-level bit flash memoryJun 10, 04Dec 15, 05[G11C]

2003/0190,786 Memory manufacturing process with bitline isolationApr 08, 02Oct 09, 03[H01L]

2002/0011,678 Method and system for providing a robust alignment mark at thin oxide layersFeb 15, 01Jan 31, 02[H01L]

2001/0052,049 Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architectureJun 26, 01Dec 13, 01[G06F]

Recent Patents

7,440,333 Method of determining voltage compensation for flash memory devicesJan 27, 06Oct 21, 08[G11C]

7,415,646 Page.sub.--EXE erase algorithm for flash memorySep 22, 04Aug 19, 08[G01R]

7,407,882 Semiconductor component having a contact structure and method of manufactureAug 27, 04Aug 05, 08[H01L]

7,307,338 Three dimensional polymer memory cell systemsJul 26, 04Dec 11, 07[H01L]

7,251,158 Erase algorithm for multi-level bit flash memoryJun 10, 04Jul 31, 07[G11C]

7,163,860 Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory deviceMay 06, 03Jan 16, 07[H01L]

7,068,204 System that facilitates reading multi-level data in non-volatile memorySep 28, 04Jun 27, 06[H03M]

7,042,766 Method of programming a flash memory device using multilevel charge storageJul 22, 04May 09, 06[G11C]

7,038,948 Read approach for multi-level virtual ground memorySep 22, 04May 02, 06[G11C]

6,974,989 Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processingMay 06, 04Dec 13, 05[H01L]

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