FUJITSU SIEMENS COMPUTERS LLC.

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Technologies

Intl Class Technology # of Patents Rank
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 8292
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 2166
 
 
 
H04J MULTIPLEX COMMUNICATION 1104

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,602,990 Computer system diagnostic testing using hardware abstractionAug 07, 95Feb 11, 97[G06F]35
5,355,471 Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sortAug 14, 92Oct 11, 94[G06F]25
5,787,095 Multiprocessor computer backlane busMar 25, 97Jul 28, 98[H04L, G06F]22
5,581,713 Multiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitrationNov 15, 95Dec 03, 96[G06F]19
6,230,286 Computer system failure reporting mechanismMar 21, 95May 08, 01[G06F]12
6,026,444 TORUS routing element error handling and self-clearing with link lockup preventionJun 24, 98Feb 15, 00[G06F]8
7,406,632 Error reporting network in multiprocessor computerJun 26, 03Jul 29, 08[G06F]3
6,408,002 Torus routing element error handling and self-clearing with missing or extraneous control code featureJun 24, 98Jun 18, 02[H04J, H04L]3
7,043,612 Compute node to mesh interface for highly scalable parallel processing system and method of exchanging dataJun 02, 03May 09, 06[G06F]1

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2004/0205,420 Error reporting network in multiprocessor computerJun 26, 03Oct 14, 04[H02H]
2004/0044,821 Compute node to mesh interface for highly scalable parallel processing system and method of exchanging dataJun 02, 03Mar 04, 04[G06F]

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
7,406,632 Error reporting network in multiprocessor computerJun 26, 03Jul 29, 08[G06F]
7,043,612 Compute node to mesh interface for highly scalable parallel processing system and method of exchanging dataJun 02, 03May 09, 06[G06F]
6,408,002 Torus routing element error handling and self-clearing with missing or extraneous control code featureJun 24, 98Jun 18, 02[H04J, H04L]
6,230,286 Computer system failure reporting mechanismMar 21, 95May 08, 01[G06F]
6,026,444 TORUS routing element error handling and self-clearing with link lockup preventionJun 24, 98Feb 15, 00[G06F]
5,787,095 Multiprocessor computer backlane busMar 25, 97Jul 28, 98[H04L, G06F]
5,602,990 Computer system diagnostic testing using hardware abstractionAug 07, 95Feb 11, 97[G06F]
5,581,713 Multiprocessor computer backplane bus in which bus transactions are classified into different classes for arbitrationNov 15, 95Dec 03, 96[G06F]
5,355,471 Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sortAug 14, 92Oct 11, 94[G06F]

Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
Myers Mark
Portland, OR
4
Lloyd Stacey
Hillsboro, OR
3
Lynch John
Portland, OR
3
Myers Mark S
Portland, OR
3
Quattromani Marc Alan
Beaverton, OR
3
Moll Jeffery L
Banks, OR
2
Myers Mark
Not Provided
2
Stout Richard
Tualatin, OR
2
Takasumi Robert
Hillsboro, OR
2
Dorwin Paul Andrew
Beaverton, OR
1