GLOBALFOUNDRIES INC.

Patent Owner

Watch Compare Add to Portfolio

Stats

Details

Patent Activity in the Last 10 Years

Technologies

Intl Class Technology MATTERS Rank in Class
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 9632 3
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 3128 22
 
 
G11C STATIC STORES 732 18
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 435 9
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 423 13
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 283 93
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 258 22
 
 
H03K PULSE TECHNIQUE 235 23
 
 
G01N INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES 168 58
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM 142 38
  • No Technologies to Display

Top Patents (by citation)

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0322,486 MODEL-BASED GENERATION OF DUMMY FEATURES Jul 25, 17 Nov 09, 17 [G03F, G06F]
2017/0323,855 LASER SCRIBE STRUCTURES FOR A WAFER May 12, 17 Nov 09, 17 [H01L]
2017/0323,902 METHOD, APPARATUS, AND SYSTEM FOR IMPROVED CELL DESIGN HAVING UNIDIRECTIONAL METAL LAYOUT ARCHITECTURE May 06, 16 Nov 09, 17 [H01L]
2017/0323,937 HIGH DENSITY CAPACITOR STRUCTURE AND METHOD Jul 27, 17 Nov 09, 17 [H01L]
2017/0324,015 THERMOELECTRIC COOLING USING THROUGH-SILICON VIAS May 05, 16 Nov 09, 17 [H01L]
2017/0324,385 METHOD, APPARATUS AND SYSTEM FOR BACK GATE BIASING FOR FD-SOI DEVICES May 06, 16 Nov 09, 17 [H03G, H03F, G06F, H01L]
2017/0324,569 Method, Apparatus and System for Security Application for Integrated Circuit Devices Jul 18, 17 Nov 09, 17 [H04L, G06F]
2017/0309,349 FAILURE ANALYSIS AND REPAIR REGISTER SHARING FOR MEMORY BIST Apr 22, 16 Oct 26, 17 [G11C]
2017/0309,522 METHODS FOR FORMING FIN STRUCTURES Jul 10, 17 Oct 26, 17 [H01L]
2017/0309,560 DEVICES AND METHODS FOR FORMING CROSS COUPLED CONTACTS Apr 22, 16 Oct 26, 17 [H01L]
2017/0309,573 INTERCONNECT STRUCTURE HAVING TUNGSTEN CONTACT COPPER WIRING Jul 11, 17 Oct 26, 17 [H01L]
2017/0309,615 METHOD, APPARATUS, AND SYSTEM FOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION Apr 21, 16 Oct 26, 17 [G05B, H01L]
2017/0309,623 METHOD, APPARATUS, AND SYSTEM FOR INCREASING DRIVE CURRENT OF FINFET DEVICE Apr 21, 16 Oct 26, 17 [H01L]
2017/0309,628 FINFET DEVICE WITH ENLARGED CHANNEL REGIONS Jul 06, 17 Oct 26, 17 [H01L]
2017/0309,643 TUNABLE CAPACITOR FOR FDSOI APPLICATIONS Jul 10, 17 Oct 26, 17 [H01L]
2017/0309,714 METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSITIONED ABOVE THE ACTIVE REGION Jun 30, 17 Oct 26, 17 [H01L]

View all publication…

  • No Publications to Display

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9812324 Methods to control fin tip placement Jan 13, 17 Nov 07, 17 [H01L]
9812336 FinFET semiconductor structures and methods of fabricating same Oct 21, 14 Nov 07, 17 [H01L]
9812351 Interconnection cells having variable width metal lines and fully-self aligned continuity cuts Dec 15, 16 Nov 07, 17 [H01L]
9812359 Thru-silicon-via structures Jun 08, 15 Nov 07, 17 [H01L]
9812365 Methods of cutting gate structures on transistor devices Oct 05, 16 Nov 07, 17 [H01L]
9812368 Method to prevent lateral epitaxial growth in semiconductor devices Oct 08, 16 Nov 07, 17 [H01L]
9812393 Programmable via devices with metal/semiconductor via links and fabrication methods thereof Sep 28, 15 Nov 07, 17 [H01L]
9812396 Interconnect structure for semiconductor devices with multiple power rails and redundancy Jun 07, 16 Nov 07, 17 [H01L]
9812400 Contact line having insulating spacer therein and method of forming same May 13, 16 Nov 07, 17 [H01L]
9812404 Electrical connection around a crackstop structure Dec 30, 15 Nov 07, 17 [H01L]
9812447 Bipolar junction transistors with extrinsic device regions free of trench isolation Feb 02, 16 Nov 07, 17 [H01L]
9812453 Self-aligned sacrificial epitaxial capping for trench silicide Feb 13, 17 Nov 07, 17 [H01L]
9812543 Common metal contact regions having different Schottky barrier heights and methods of manufacturing same Mar 04, 16 Nov 07, 17 [H01L]
9812573 Semiconductor structure including a transistor having stress creating regions and method for the formation thereof May 13, 16 Nov 07, 17 [H01L]
9812575 Contact formation for stacked FinFETs Sep 15, 16 Nov 07, 17 [H01L]
9812638 Backend of line (BEOL) compatible high current density access device for high density arrays of electronic components Mar 19, 10 Nov 07, 17 [H01L]
9804231 Power noise histogram of a computer system Apr 07, 14 Oct 31, 17 [G01R, G06F]
9805949 High κ gate stack on III-V compound semiconductors Sep 09, 12 Oct 31, 17 [H01L]
9805972 Skip via structures Feb 20, 17 Oct 31, 17 [H01L]
9805977 Integrated circuit structure having through-silicon via and method of forming same Jun 08, 16 Oct 31, 17 [H01L]
9805982 Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs May 17, 16 Oct 31, 17 [H01L]
9805988 Method of forming semiconductor structure including suspended semiconductor layer and resulting structure Dec 01, 16 Oct 31, 17 [H01L]
9805990 FDSOI voltage reference Jun 26, 15 Oct 31, 17 [H01L, G05F]
9806025 SOI wafers with buried dielectric layers to prevent Cu diffusion Dec 29, 15 Oct 31, 17 [H01L]
9806032 Integrated circuit structure with refractory metal alignment marker and methods of forming same Dec 20, 16 Oct 31, 17 [H01L]
9806067 Die-die stacking Jul 20, 15 Oct 31, 17 [H01L]
9806078 FinFET spacer formation on gate sidewalls, between the channel and source/drain regions Nov 02, 16 Oct 31, 17 [H01L]
9806161 Integrated circuit structure having thin gate dielectric device and thick gate dielectric device Apr 07, 16 Oct 31, 17 [H01L]
9806170 Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI May 11, 16 Oct 31, 17 [H01L]
9806221 Germanium photodetector with SOI doping source Feb 24, 17 Oct 31, 17 [H01L]
9806701 Digital frequency multiplier to generate a local oscillator signal in FDSOI technology Dec 09, 16 Oct 31, 17 [H04W, H01L, H04B, H03K, H03L]

View all Patent…

  • No Patents to Display

Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2017/0294,354 INTEGRATION OF NOMINAL GATE WIDTH FINFETS AND DEVICES HAVING LARGER GATE WIDTH ABAN Apr 07, 16 Oct 12, 17 [H01L]
2017/0207,118 SELF-ALIGNED SOURCE/DRAIN CONTACT IN REPLACEMENT METAL GATE PROCESS ABAN Jan 14, 16 Jul 20, 17 [H01L]
2017/0125,288 ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS ABAN Jan 17, 17 May 04, 17 [H01L]
2017/0077,234 DEVICES AND METHODS OF CREATING ELASTIC RELAXATION OF EPITAXIALLY GROWN LATTICE MISMATCHED FILMS ABAN Sep 14, 15 Mar 16, 17 [H01L]
2017/0033,181 METHODS OF FORMING REPLACEMENT FINS COMPRISED OF MULTIPLE LAYERS OF DIFFERENT SEMICONDUCTOR MATERIALS ABAN Jul 28, 15 Feb 02, 17 [H01L]
2017/0025,347 METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION ABAN Feb 12, 16 Jan 26, 17 [H01L]
2016/0377,448 PREDICTING AND ALERTING USER TO NAVIGATION OPTIONS AND PREDICTING USER INTENTIONS ABAN Jun 29, 15 Dec 29, 16 [G06N, G01C]
2016/0379,818 INSULATING A VIA IN A SEMICONDUCTOR SUBSTRATE ABAN Jun 25, 15 Dec 29, 16 [H01L]
2016/0380,095 HIGH VOLTAGE FINFET STRUCTURE WITH SHAPED DRIFT REGION ABAN Jun 25, 15 Dec 29, 16 [H01L]
2016/0372,413 UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME ABAN Jun 17, 15 Dec 22, 16 [H01L]
2016/0351,675 INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATE ELECTRODES ABAN May 26, 15 Dec 01, 16 [H01L]
2016/0336,172 LITHOGRAPHY STACK AND METHOD ABAN May 14, 15 Nov 17, 16 [G03F, H01L]
2016/0329,278 2D SELF-ALIGNED VIA FIRST PROCESS FLOW ABAN Apr 21, 16 Nov 10, 16 [H01L]
2016/0306,678 Automatic Analytical Cloud Scaling of Hardware Using Resource Sub-Cloud ABAN Jun 03, 15 Oct 20, 16 [G06F]
2016/0293,706 FINFET SEMICONDUCTOR DEVICES WITH STRESSED CHANNEL REGIONS ABAN Jun 20, 16 Oct 06, 16 [H01L]
2016/0284,392 MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AND METHOD INCLUDING READ AND WRITE OPERATIONS AT A MEMORY CELL ABAN Mar 24, 15 Sep 29, 16 [G11C]
2016/0284,846 FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE ABAN Mar 25, 15 Sep 29, 16 [H01L]
2016/0276,345 ELIMINATING FIELD OXIDE LOSS PRIOR TO FINFET SOURCE/DRAIN EPITAXIAL GROWTH ABAN Feb 22, 16 Sep 22, 16 [H01L]
2016/0276,428 HIGH-VOLTAGE TRANSISTOR DEVICE ABAN Mar 16, 15 Sep 22, 16 [H01L, H03K]
2016/0268,378 INTEGRATED STRAINED FIN AND RELAXED FIN ABAN Mar 12, 15 Sep 15, 16 [H01L]

View all Patent…

  • No Patents to Display

Top Inventors for This Owner

We are sorry but your current selection exceeds the maximum number of watches () for this membership level. Upgrade to our Level for up to watches!

Owner Watch
GLOBALFOUNDRIES INC.
CANCEL
UPGRADE MEMBERSHIP CANCEL

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to comparisons!

UPGRADE MEMBERSHIP CANCEL

We are sorry but your current selection exceeds the maximum number of portfolios () for this membership level. Upgrade to our Level for up to portfolios!

UPGRADE MEMBERSHIP CANCEL

We are sorry but your current selection exceeds the maximum number of patents allowed in portfolios () for this membership level. Upgrade to our Level for up to patents!

UPGRADE MEMBERSHIP CANCEL