GLOBALFOUNDRIES INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology MATTERS Rank in Class
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 9842 3
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 3130 23
 
 
G11C STATIC STORES 742 18
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 440 10
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 427 13
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 281 95
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 257 22
 
 
H03K PULSE TECHNIQUE 237 23
 
 
G01N INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES 168 63
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM 141 43
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Top Patents (by citation)

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2018/0075,921 WORD LINE VOLTAGE GENERATOR FOR PROGRAMMABLE MEMORY ARRAY Oct 23, 17 Mar 15, 18 [G11C]
2018/0076,082 FORMING AIR GAP Nov 15, 17 Mar 15, 18 [H01L]
2018/0076,110 BACKSIDE SPACER STRUCTURES FOR IMPROVED THERMAL PERFORMANCE Sep 14, 16 Mar 15, 18 [H01L]
2018/0076,299 EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS Nov 17, 17 Mar 15, 18 [H01L]
2018/0067,396 FORMING EDGE ETCH PROTECTION USING DUAL LAYER OF POSITIVE-NEGATIVE TONE RESISTS Sep 02, 16 Mar 08, 18 [G03F]
2018/0068,858 FORMING A CONTACT FOR A TALL FIN TRANSISTOR Nov 02, 17 Mar 08, 18 [H01L]
2018/0068,993 THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES Oct 31, 17 Mar 08, 18 [H01L]
2018/0069,005 PUNCHTHROUGH STOP LAYERS FOR FIN-TYPE FIELD-EFFECT TRANSISTORS Sep 08, 16 Mar 08, 18 [H01L]
2018/0069,009 SELECTIVE SAC CAPPING ON FIN FIELD EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS Sep 08, 16 Mar 08, 18 [H01L]
2018/0069,091 METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFORMANCE AND HCI OPTIMIZATION Sep 02, 16 Mar 08, 18 [H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9922883 Method for making strained semiconductor device and related methods Jun 13, 16 Mar 20, 18 [H01L]
9922929 Self aligned interconnect structures Nov 29, 16 Mar 20, 18 [H01L]
9922972 Embedded silicon carbide block patterning Apr 19, 17 Mar 20, 18 [H01L]
9922973 Switches with deep trench depletion and isolation structures Jun 01, 17 Mar 20, 18 [H01L]
9922986 Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof May 16, 16 Mar 20, 18 [H01L]
9923046 Semiconductor device resistor structure Sep 21, 16 Mar 20, 18 [H01L]
9923076 Gate patterning for AC and DC performance boost Jun 17, 16 Mar 20, 18 [H01L]
9923078 Trench silicide contacts with high selectivity process Oct 30, 15 Mar 20, 18 [H01L]
9923082 Junction butting structure using nonuniform trench shape Mar 09, 17 Mar 20, 18 [H01L]
9923527 Method, apparatus and system for back gate biasing for FD-SOI devices May 06, 16 Mar 20, 18 [H03G, H03F, G06F, H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2018/0046,072 AUTOMATED FULL-CHIP DESIGN SPACE SAMPLING USING UNSUPERVISED MACHINE LEARNING ABAN Aug 10, 16 Feb 15, 18 [G06N, G03F, G06F]
2018/0012,791 INTERCONNECTS WITH INNER SACRIFICIAL SPACERS ABAN Jul 06, 16 Jan 11, 18 [H01L]
2017/0373,071 VERTICAL CHANNEL TRANSISTOR-BASED SEMICONDUCTOR STRUCTURE ABAN Jun 27, 16 Dec 28, 17 [H01L]
2017/0365,504 FORMING AIR GAP ABAN Jun 20, 16 Dec 21, 17 [H01L]
2017/0345,912 METHODS OF RECESSING A GATE STRUCTURE USING OXIDIZING TREATMENTS DURING A RECESSING ETCH PROCESS ABAN May 26, 16 Nov 30, 17 [H01L]
2017/0338,343 HIGH-VOLTAGE TRANSISTOR DEVICE ABAN May 23, 16 Nov 23, 17 [H01L]
2017/0330,878 NOVEL METHOD TO FABRICATE VERTICAL NWs ABAN May 13, 16 Nov 16, 17 [H01L]
2017/0294,354 INTEGRATION OF NOMINAL GATE WIDTH FINFETS AND DEVICES HAVING LARGER GATE WIDTH ABAN Apr 07, 16 Oct 12, 17 [H01L]
2017/0288,041 METHOD FOR FORMING A DOPED REGION IN A FIN USING A VARIABLE THICKNESS SPACER AND THE RESULTING DEVICE ABAN Apr 05, 16 Oct 05, 17 [H01L]
2017/0207,118 SELF-ALIGNED SOURCE/DRAIN CONTACT IN REPLACEMENT METAL GATE PROCESS ABAN Jan 14, 16 Jul 20, 17 [H01L]
2017/0200,786 FABRICATION OF TRANSISTOR-BASED SEMICONDUCTOR DEVICE USING CLOSED-LOOP FINS ABAN Jan 12, 16 Jul 13, 17 [H01L]
2017/0162,430 METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AIR GAPS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS ABAN Dec 03, 15 Jun 08, 17 [H01L]
2017/0154,687 SRAM-LIKE EBI STRUCTURE DESIGN AND IMPLEMENTATION TO CAPTURE MOSFET SOURCE-DRAIN LEAKAGE EARILER ABAN Nov 30, 15 Jun 01, 17 [G11C, H01L]
2017/0125,288 ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS ABAN Jan 17, 17 May 04, 17 [H01L]
2017/0077,234 DEVICES AND METHODS OF CREATING ELASTIC RELAXATION OF EPITAXIALLY GROWN LATTICE MISMATCHED FILMS ABAN Sep 14, 15 Mar 16, 17 [H01L]
2017/0069,518 ELECTROSTATIC SUBSTRATE HOLDER WITH NON-PLANAR SURFACE AND METHOD OF ETCHING ABAN Sep 04, 15 Mar 09, 17 [H01L]
2017/0062,438 ELECTRICAL GATE-TO-SOURCE/DRAIN CONNECTION ABAN May 05, 16 Mar 02, 17 [H01L]
2017/0033,061 MITIGATING TRANSIENT TSV-INDUCED IC SUBSTRATE NOISE AND RESULTING DEVICES ABAN Jul 29, 15 Feb 02, 17 [H01L]
2017/0033,181 METHODS OF FORMING REPLACEMENT FINS COMPRISED OF MULTIPLE LAYERS OF DIFFERENT SEMICONDUCTOR MATERIALS ABAN Jul 28, 15 Feb 02, 17 [H01L]
2017/0025,347 METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION ABAN Feb 12, 16 Jan 26, 17 [H01L]

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