GLOBALFOUNDRIES INC.
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- 0 15,845 US PATENTS IN FORCE
- 205 US APPLICATIONS PENDING
- Mar 20, 2018 most recent publication
Details
- 15,845 Issued Patents
- 0 Issued in last 3 years
- 0 Published in last 3 years
- 403,703 Total Citation Count
- Nov 01, 1984 Earliest Filing
- 5,825 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
Technologies
Intl Class
Technology
MATTERS
Rank in Class
Intl Class
Technology
MATTERS
Rank in Class
- No Technologies to Display
Top Patents (by citation)
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Patent #
Title
Filing Date
Issue Date
Intl Class
CITATIONS
5640343
Magnetic memory array using magnetic tunnel junction devices in the memory cells
Mar 18, 96
Jun 17, 97
[G11C]
762
6706571
Method for forming multiple structures in a semiconductor device
Oct 22, 02
Mar 16, 04
[H01L]
539
6475869
Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
Feb 26, 01
Nov 05, 02
[H01L]
501
6271823
Reflective electrophoretic display with laterally adjacent color cells using a reflective panel
Sep 16, 98
Aug 07, 01
[G09G, G02B]
398
6599778
Chip and wafer integration process using vertical connections
Dec 19, 01
Jul 29, 03
[H01L]
382
6528409
Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
Apr 29, 02
Mar 04, 03
[H01L]
377
- No Patents to Display
Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2018/0075,921
WORD LINE VOLTAGE GENERATOR FOR PROGRAMMABLE MEMORY ARRAY
Oct 23, 17
Mar 15, 18
[G11C]
2018/0061,699
MULTIPLE PATTERNING PROCESS FOR FORMING PILLAR MASK ELEMENTS
Aug 31, 16
Mar 01, 18
[H01L]
2018/0053,662
TEXTURING OF SILICON SURFACE WITH DIRECT-SELF ASSEMBLY PATTERNING
Aug 17, 16
Feb 22, 18
[H01L]
2018/0053,789
COMPENSATION OF TEMPERATURE EFFECTS IN SEMICONDUCTOR DEVICE STRUCTURES
Oct 31, 17
Feb 22, 18
[H01L]
2018/0053,829
METHOD OF FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Aug 22, 16
Feb 22, 18
[H01L]
2018/0047,564
METHOD TO TUNE CONTACT CD AND REDUCE MASK COUNT BY TILTED ION BEAM
Aug 10, 16
Feb 15, 18
[H01L]
2018/0040,477
OXIDIZING FILLER MATERIAL LINES TO INCREASE WIDTH OF HARD MASK LINES
Oct 04, 17
Feb 08, 18
[H01L]
2018/0040,505
METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE USING A NITRIDE LINER AND A DIFFUSIONLESS ANNEAL
Aug 02, 16
Feb 08, 18
[H01L]
- No Publications to Display
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
9922883
Method for making strained semiconductor device and related methods
Jun 13, 16
Mar 20, 18
[H01L]
9922986
Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and method for the formation thereof
May 16, 16
Mar 20, 18
[H01L]
9923527
Method, apparatus and system for back gate biasing for FD-SOI devices
May 06, 16
Mar 20, 18
[H01L, G06F, H03F, H03G]
- No Patents to Display
Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
2018/0046,072
AUTOMATED FULL-CHIP DESIGN SPACE SAMPLING USING UNSUPERVISED MACHINE LEARNING
Abandoned
Aug 10, 16
Feb 15, 18
[G06N, G06F, G03F]
2017/0373,071
VERTICAL CHANNEL TRANSISTOR-BASED SEMICONDUCTOR STRUCTURE
Abandoned
Jun 27, 16
Dec 28, 17
[H01L]
2017/0345,912
METHODS OF RECESSING A GATE STRUCTURE USING OXIDIZING TREATMENTS DURING A RECESSING ETCH PROCESS
Abandoned
May 26, 16
Nov 30, 17
[H01L]
2017/0294,354
INTEGRATION OF NOMINAL GATE WIDTH FINFETS AND DEVICES HAVING LARGER GATE WIDTH
Abandoned
Apr 07, 16
Oct 12, 17
[H01L]
2017/0288,041
METHOD FOR FORMING A DOPED REGION IN A FIN USING A VARIABLE THICKNESS SPACER AND THE RESULTING DEVICE
Abandoned
Apr 05, 16
Oct 05, 17
[H01L]
2017/0207,118
SELF-ALIGNED SOURCE/DRAIN CONTACT IN REPLACEMENT METAL GATE PROCESS
Abandoned
Jan 14, 16
Jul 20, 17
[H01L]
2017/0200,786
FABRICATION OF TRANSISTOR-BASED SEMICONDUCTOR DEVICE USING CLOSED-LOOP FINS
Abandoned
Jan 12, 16
Jul 13, 17
[H01L]
2017/0162,430
METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AIR GAPS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS
Abandoned
Dec 03, 15
Jun 08, 17
[H01L]
2017/0154,687
SRAM-LIKE EBI STRUCTURE DESIGN AND IMPLEMENTATION TO CAPTURE MOSFET SOURCE-DRAIN LEAKAGE EARILER
Abandoned
Nov 30, 15
Jun 01, 17
[H01L, G11C]
2017/0125,288
ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS
Abandoned
Jan 17, 17
May 04, 17
[H01L]
2017/0077,234
DEVICES AND METHODS OF CREATING ELASTIC RELAXATION OF EPITAXIALLY GROWN LATTICE MISMATCHED FILMS
Abandoned
Sep 14, 15
Mar 16, 17
[H01L]
2017/0069,518
ELECTROSTATIC SUBSTRATE HOLDER WITH NON-PLANAR SURFACE AND METHOD OF ETCHING
Abandoned
Sep 04, 15
Mar 09, 17
[H01L]
2017/0033,061
MITIGATING TRANSIENT TSV-INDUCED IC SUBSTRATE NOISE AND RESULTING DEVICES
Abandoned
Jul 29, 15
Feb 02, 17
[H01L]
2017/0033,181
METHODS OF FORMING REPLACEMENT FINS COMPRISED OF MULTIPLE LAYERS OF DIFFERENT SEMICONDUCTOR MATERIALS
Abandoned
Jul 28, 15
Feb 02, 17
[H01L]
2017/0025,347
METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION
Abandoned
Feb 12, 16
Jan 26, 17
[H01L]
2017/0019,982
METHOD, APPARATUS AND SYSTEM FOR PROVIDING MULTIPLE EUV BEAMS FOR SEMICONDUCTOR PROCESSING
Abandoned
Jul 18, 15
Jan 19, 17
[G21K, H05G]
- No Patents to Display
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