INVENSAS CORPORATION

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Technologies

Intl Class Technology # of Patents Rank
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 24894
 
 
 
G11C STATIC STORES 7371
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3568
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 31269
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2248
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1025
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 9105
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 8120
 
 
 
H01K ELECTRIC INCANDESCENT LAMPS 715
 
 
 
H03K PULSE TECHNIQUE 6100

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,487,218 Method for making printed circuit boards with selectivity filled plated through holesNov 21, 94Jan 30, 96[H01K]182
6,322,903 Package of integrated circuits and vertical integrationDec 06, 99Nov 27, 01[H01L]171
5,611,140 Method of forming electrically conductive polymer interconnects on electrical substratesFeb 10, 95Mar 18, 97[H05K]145
6,184,060 Integrated circuits and methods for their fabricationMay 22, 98Feb 06, 01[H01L]135
5,545,923 Semiconductor device assembly with minimized bond finger connectionsFeb 28, 95Aug 13, 96[H01L]134
6,057,598 Face on face flip chip integrationJan 31, 97May 02, 00[H01L]128
5,562,801 Method of etching an oxide layerDec 07, 94Oct 08, 96[H01L]127
6,335,571 Semiconductor flip-chip package and method for the fabrication thereofMar 02, 00Jan 01, 02[H01L]116
5,468,342 Method of etching an oxide layerApr 28, 94Nov 21, 95[B44C, C03C, H01L]115
6,221,735 Method for eliminating stress induced dislocations in CMOS devicesFeb 15, 00Apr 24, 01[H01L]114

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0107,630 NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIVE COUPLINGOct 28, 11May 02, 13[G11C, H01L]
2013/0107,635 COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIBLE NON-VOLATILE MEMORY CELLOct 28, 11May 02, 13[G11C]
2013/0099,387 MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOFOct 20, 11Apr 25, 13[H01L]
2013/0099,392 Support mounted electrically interconnected die assemblyApr 25, 12Apr 25, 13[H01L]
2013/0093,087 PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIASFeb 24, 12Apr 18, 13[H01L]
2013/0093,088 PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIASFeb 24, 12Apr 18, 13[H01L]
2013/0095,610 PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIASFeb 24, 12Apr 18, 13[H01L]
2013/0082,374 STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATEApr 04, 12Apr 04, 13[H01L]
2013/0082,375 STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATEApr 04, 12Apr 04, 13[H01L]
2013/0082,380 STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATEApr 04, 12Apr 04, 13[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,436,457 Stub minimization for multi-die wirebond assemblies with parallel windowsDec 27, 11May 07, 13[H01L]
8,436,477 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrateApr 04, 12May 07, 13[H01L]
8,431,431 Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layersJul 12, 11Apr 30, 13[H01L]
8,404,520 Package-on-package assembly with wire bond viasFeb 24, 12Mar 26, 13[H01L]
8,405,196 Chips having rear contacts connected by through vias to front contactsFeb 26, 08Mar 26, 13[H01L]
8,405,207 Stub minimization for wirebond assemblies without windowsApr 05, 12Mar 26, 13[H01L]
8,372,741 Method for package-on-package assembly with wire bonds to encapsulation surfaceFeb 24, 12Feb 12, 13[H01L]
8,357,999 Assembly having stacked die mounted on substrateMay 03, 07Jan 22, 13[H01L]
8,345,441 Stub minimization for multi-die wirebond assemblies with parallel windowsDec 27, 11Jan 01, 13[H01R]
8,324,081 Wafer level surface passivation of stackable integrated circuit chipsMar 04, 11Dec 04, 12[H01L]

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Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
Leung Wingyu
Cupertino, CA
46
Siniaguine Oleg
San Carlos, CA
38
Haba Belgacem
Saratoga, CA
37
Savastiouk Sergey
San Jose, CA
30
Parris Michael C
Colorado Springs, CO
28
Iijima Tomoo
Tokyo, JP
26
Crisp Richard Dewitt
Not Provided
25
Zohni Wael
Not Provided
25
Lambrecht Frank
Not Provided
20
Oganesian Vage
Palo Alto, CA
20