INVENSAS CORPORATION

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 44985
 
 
 
G11C STATIC STORES 8470
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 6675
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 35360
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2161
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 12105
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1133
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 9132
 
 
 
H01K ELECTRIC INCANDESCENT LAMPS 716
 
 
 
H03K PULSE TECHNIQUE 6109

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0206,815 FINE PITCH BVA USING RECONSTITUTED WAFER WITH AREA ARRAY ACCESSIBLE FOR TESTINGJan 17, 14Jul 23, 15[H01L]
2015/0198,971 Stub minimization for multi-die wirebond assemblies with parallel windowsMar 16, 15Jul 16, 15[G06F]
2015/0187,673 REDUCED STRESS TSV AND INTERPOSER STRUCTURESMar 10, 15Jul 02, 15[H01L]
2015/0187,730 STACKABLE MICROELECTRONIC PACKAGE STRUCTURESMar 16, 15Jul 02, 15[H01L]
2015/0179,619 STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGEDec 22, 14Jun 25, 15[H01L]
2015/0171,027 HIGH YIELD SUBSTRATE ASSEMBLYAug 23, 14Jun 18, 15[H01L]
2015/0171,265 QUANTUM EFFICIENCY OF MULTIPLE QUANTUM WELLSFeb 23, 15Jun 18, 15[H01L]
2015/0162,216 TUNABLE COMPOSITE INTERPOSERFeb 23, 15Jun 11, 15[H01L]
2015/0162,241 METAL PVD-FREE CONDUCTING STRUCTURESFeb 20, 15Jun 11, 15[H01L]
2015/0155,230 CARRIER-LESS SILICON INTERPOSER USING PHOTO PATTERNED POLYMER AS SUBSTRATEDec 04, 13Jun 04, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,087,815 Off substrate kinking of bond wireNov 12, 13Jul 21, 15[B23K, H01L]
9,082,753 Severing bond wire by kinking and twistingJun 06, 14Jul 14, 15[B23K, H01L]
9,076,594 Capacitors using porous alumina structuresMar 12, 13Jul 07, 15[H01G, H01L, H01M]
9,076,785 Method and structures for via substrate repair and assemblyDec 11, 12Jul 07, 15[H01L]
9,070,423 Single package dual channel memory with co-supportNov 08, 13Jun 30, 15[G11C, H01L]
9,070,676 Bowl-shaped solder structureOct 09, 13Jun 30, 15[H01L]
9,070,849 Parallel plate slot emission arrayOct 18, 13Jun 30, 15[H01L]
9,064,933 Methods and structure for carrier-less thin wafer handlingDec 21, 12Jun 23, 15[H01L]
9,059,181 Wafer leveled chip packaging structure and method thereofNov 18, 13Jun 16, 15[H01L]
9,041,227 Package-on-package assembly with wire bond viasMar 12, 13May 26, 15[H01L, H05K]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEABANMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERABANMar 12, 13Jul 25, 13[H01L]
2013/0119,117 BONDING WEDGEABANNov 02, 12May 16, 13[H01L]
2013/0070,437 HYBRID INTERPOSERABANSep 20, 11Mar 21, 13[H01R, H05K]
2013/0068,516 HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIASABANSep 19, 11Mar 21, 13[H05K]
2013/0037,312 HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATIONABANAug 10, 11Feb 14, 13[B05D, B32B, H05K]
2011/0197,655 MULTI-LAYERED CERAMIC MICRO-GAS CHROMATOGRAPH AND METHOD FOR MAKING THE SAMEABANDec 07, 10Aug 18, 11[G01N]
7,856,444 Performing a search using a search parameterExpiredDec 27, 04Dec 21, 10[G06F]
7,843,046 Flat leadless packages and stacked leadless package assembliesExpiredAug 27, 08Nov 30, 10[H01L]
2010/0242,270 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit moduleABANFeb 16, 10Sep 30, 10[H01K]
2010/0071,944 CHIP CAPACITOR EMBEDDED PWBABANDec 17, 07Mar 25, 10[H05K]
2010/0044,860 Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layerABANJul 30, 09Feb 25, 10[H01L]
2009/0106,488 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKSABANOct 20, 08Apr 23, 09[G06F]
2009/0071,707 Multilayer substrate with interconnection vias and method of manufacturing the sameABANAug 13, 08Mar 19, 09[H05K, C25D]
2008/0296,254 Multilayer wiring board for an electronic deviceABANJan 11, 08Dec 04, 08[C23F]
2008/0264,678 Member for Interconnecting Wiring Films and Method for Producing the SameABANSep 06, 05Oct 30, 08[H05K]
2008/0169,568 Structure and method of making interconnect element having metal traces embedded in surface of dielectricABANAug 29, 07Jul 17, 08[H01L]
2008/0136,041 Structure and method of making interconnect element having metal traces embedded in surface of dielectricABANMay 23, 07Jun 12, 08[H01L]
2008/0128,288 Method of manufacturing a multi-layer wiring board using a metal member having a rough surfaceABANJun 08, 07Jun 05, 08[C25D]
2007/0221,329 Apparatus and method for distributing a liquid onto a surface of an itemABANOct 23, 06Sep 27, 07[B44C, H01L]

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