INVENSAS CORPORATION

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 63171
 
 
 
G11C STATIC STORES 11265
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 8476
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 39398
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2367
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 12146
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 11125
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1038
 
 
 
B81C PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS 723
 
 
 
H03K PULSE TECHNIQUE 7120

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0236,794 Multichip modules and methods of fabricationMay 02, 17Aug 17, 17[H01L]
2017/0212,848 Method for Reduced Load Memory ModuleApr 06, 17Jul 27, 17[G06F]
2017/0207,159 POROUS ALUMINA TEMPLATES FOR ELECTRONIC PACKAGESApr 03, 17Jul 20, 17[H01L]
2017/0200,696 MULTI-CHIP PACKAGE WITH INTERCONNECTS EXTENDING THROUGH LOGIC CHIPJan 19, 17Jul 13, 17[H01L]
2017/0200,877 LIGHT EMITTING DIODE DEVICE WITH RECONSTITUTED LED COMPONENTS ON SUBSTRATEMar 25, 17Jul 13, 17[G01R, H01L]
2017/0194,279 STRUCTURES AND METHODS FOR LOW TEMPERATURE BONDING USING NANOPARTICLESMar 17, 17Jul 06, 17[H01L]
2017/0194,281 Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfacesJan 18, 16Jul 06, 17[H01L]
2017/0194,373 METHOD OF FABRICATING LOW CTE INTERPOSER WITHOUT TSV STRUCTUREJan 17, 17Jul 06, 17[H01L]
2017/0178,958 METHOD AND STRUCTURES FOR VIA SUBSTRATE REPAIR AND ASSEMBLYMar 08, 17Jun 22, 17[H01L]
2017/0179,046 HIGH YIELD SUBSTRATE ASSEMBLYMar 05, 17Jun 22, 17[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9735084 Bond via array for thermal conductivityDec 11, 14Aug 15, 17[H01L]
9728495 Reconfigurable PoPMar 10, 14Aug 08, 17[G11C, H01L]
9728524 Enhanced density assembly having microelectronic packages mounted at substantial angle to boardJun 30, 16Aug 08, 17[H01L, H05K]
9728527 Multiple bond via arrays of different wire heights on a same substrateOct 28, 15Aug 08, 17[H01L]
9711401 Reliable packaging and interconnect structuresJun 28, 16Jul 18, 17[H01L]
9705497 On-chip impedance network with digital coarse and analog fine tuningAug 18, 15Jul 11, 17[H01C, H03F, G11C, H03K, H03L]
9698131 Methods of forming 3-D circuits with integrated passive devicesDec 21, 15Jul 04, 17[H01L]
9691437 Compact microelectronic assembly having reduced spacing between controller and memory packagesSep 25, 14Jun 27, 17[G11C, H01L]
9691679 Method for package-on-package assembly with wire bonds to encapsulation surfaceMay 19, 16Jun 27, 17[H01L]
9691693 Carrier-less silicon interposer using photo patterned polymer as substrateDec 04, 13Jun 27, 17[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
9496242 Stackable microelectronic package structuresWithdrawnMar 16, 15Nov 15, 16[B81C, H01L]
2016/0260,671 MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURESABANMay 17, 16Sep 08, 16[H01L]
9418879 Low cost interposer and method of fabricationWithdrawnMar 14, 13Aug 16, 16[H01L]
2015/0371,938 BACK-END-OF-LINE STACK FOR A STACKED DEVICEABANJun 19, 14Dec 24, 15[H01L]
2015/0295,151 HIGH PERFORMANCE LIGHT EMITTING DIODE WITH VIASABANAug 23, 14Oct 15, 15[H01L]
2015/0262,902 INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTUREABANMar 14, 14Sep 17, 15[H01L]
9117827 Making electrical components in handle wafers of integrated circuit packagesWithdrawnMay 02, 14Aug 25, 15[H01L]
2015/0171,027 HIGH YIELD SUBSTRATE ASSEMBLYABANAug 23, 14Jun 18, 15[H01L]
2015/0076,714 MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION SURFACEABANSep 16, 13Mar 19, 15[H01L]
2015/0056,753 Semiconductor Die Having Fine Pitch Electrical InterconnectsABANSep 08, 14Feb 26, 15[H01L]
2014/0008,676 OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICESABANJul 03, 12Jan 09, 14[H01L]
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEABANMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERABANMar 12, 13Jul 25, 13[H01L]
2013/0119,012 INTERCONNECTION ELEMENT FOR ELECTRIC CIRCUITSABANOct 26, 12May 16, 13[H01R]
2013/0119,117 BONDING WEDGEABANNov 02, 12May 16, 13[H01L]
8405196 Chips having rear contacts connected by through vias to front contactsExpiredFeb 26, 08Mar 26, 13[H01L]
2013/0070,437 HYBRID INTERPOSERABANSep 20, 11Mar 21, 13[H01R, H05K]
2013/0068,516 HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIASABANSep 19, 11Mar 21, 13[H05K]
2013/0037,312 HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATIONABANAug 10, 11Feb 14, 13[B05D, B32B, H05K]
8357999 Assembly having stacked die mounted on substrateExpiredMay 03, 07Jan 22, 13[H01L]

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