INVENSAS CORPORATION

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 61969
 
 
 
G11C STATIC STORES 10667
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 8273
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 38398
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2465
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1235
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 11149
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 10125
 
 
 
B81C PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS 720
 
 
 
H03K PULSE TECHNIQUE 7122

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0162,491 Chip-size, double side connection package and method for manufacturing the sameOct 14, 13Jun 08, 17[H01L]
2017/0154,875 Multiple bond via arrays of different wire heights on a same substrateFeb 13, 17Jun 01, 17[B81B, H01L]
2017/0148,696 FINE PITCH BVA USING RECONSTITUTED WAFER WITH AREA ARRAY ACCESSIBLE FOR TESTINGFeb 02, 17May 25, 17[H01L]
2017/0148,763 HYBRID 3D/2.5D INTERPOSERNov 25, 15May 25, 17[H01L]
2017/0141,042 'RDL-First' Packaged Microelectronic Device for a Package-on-Package DeviceNov 16, 16May 18, 17[H01L]
2017/0141,083 Packaged Microelectronic Device for a Package-on-Package DeviceNov 16, 16May 18, 17[H01L]
2017/0141,094 MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOFJan 30, 17May 18, 17[H01L]
2017/0133,081 HIGH-BANDWIDTH MEMORY APPLICATION WITH CONTROLLED IMPEDANCE LOADINGOct 28, 16May 11, 17[G11C, H01L]
2017/0125,331 INTERCONNECTION SUBSTRATES FOR INTERCONNECTION BETWEEN CIRCUIT MODULES, AND METHODS OF MANUFACTUREJan 11, 17May 04, 17[H01L]
2017/0117,030 DRAM Adjacent Row Disturb MitigationFeb 09, 16Apr 27, 17[G11C]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9673124 Device and method for localized underfillMay 10, 16Jun 06, 17[H01L]
9666513 Wafer-level flipped die stacks with leadframes or metal foil interconnectsNov 03, 16May 30, 17[H01L]
9666514 High performance compliant substrateApr 14, 15May 30, 17[H01L, H05K]
9666521 Ultra high performance interposerAug 08, 13May 30, 17[H01L]
9666559 Multichip modules and methods of fabricationJul 24, 15May 30, 17[B81C, B81B, H01L]
9666560 Multi-chip microelectronic assembly with built-up fine-patterned circuit structureNov 25, 15May 30, 17[H01L]
9659848 Stiffened wires for offset BVAMar 31, 16May 23, 17[H01L]
9646917 Low CTE component with wire bond interconnectsMay 29, 14May 09, 17[H01L]
9646946 Fan-out wafer-level packaging using metal foil laminationOct 07, 15May 09, 17[H01L]
9640236 Reduced load memory module using wire bonds and a plurality of rank signalsMar 12, 15May 02, 17[G11C, G06F]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
9496242 Stackable microelectronic package structuresWithdrawnMar 16, 15Nov 15, 16[B81C, H01L]
9418879 Low cost interposer and method of fabricationWithdrawnMar 14, 13Aug 16, 16[H01L]
2015/0262,902 INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTUREABANMar 14, 14Sep 17, 15[H01L]
9117827 Making electrical components in handle wafers of integrated circuit packagesWithdrawnMay 02, 14Aug 25, 15[H01L]
2015/0171,027 HIGH YIELD SUBSTRATE ASSEMBLYABANAug 23, 14Jun 18, 15[H01L]
2015/0076,714 MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION SURFACEABANSep 16, 13Mar 19, 15[H01L]
2014/0008,676 OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICESABANJul 03, 12Jan 09, 14[H01L]
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEABANMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERABANMar 12, 13Jul 25, 13[H01L]
2013/0119,012 INTERCONNECTION ELEMENT FOR ELECTRIC CIRCUITSABANOct 26, 12May 16, 13[H01R]
2013/0119,117 BONDING WEDGEABANNov 02, 12May 16, 13[H01L]
2013/0070,437 HYBRID INTERPOSERABANSep 20, 11Mar 21, 13[H01R, H05K]
2013/0068,516 HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIASABANSep 19, 11Mar 21, 13[H05K]
2013/0037,312 HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATIONABANAug 10, 11Feb 14, 13[B05D, B32B, H05K]
8310036 Chips having rear contacts connected by through vias to front contactsExpiredMay 21, 10Nov 13, 12[H01L]
8119516 Bump structure formed from using removable mandrelExpiredNov 04, 08Feb 21, 12[H01L]
8112881 Method for manufacturing multilayer wiring boardExpiredSep 29, 05Feb 14, 12[H05K]
2011/0197,655 MULTI-LAYERED CERAMIC MICRO-GAS CHROMATOGRAPH AND METHOD FOR MAKING THE SAMEABANDec 07, 10Aug 18, 11[G01N]
7856444 Performing a search using a search parameterExpiredDec 27, 04Dec 21, 10[G06F]
7843046 Flat leadless packages and stacked leadless package assembliesExpiredAug 27, 08Nov 30, 10[H01L]

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