INVENSAS CORPORATION

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 58071
 
 
 
G11C STATIC STORES 10466
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 7679
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 38388
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2563
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1135
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 10149
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 10118
 
 
 
H03K PULSE TECHNIQUE 7118
 
 
 
H01K ELECTRIC INCANDESCENT LAMPS 617

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0343,613 THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICONMay 17, 16Nov 24, 16[H01L]
2016/0336,286 CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTUREJul 27, 16Nov 17, 16[H01L, H05K]
2016/0329,290 Reliable Device AssemblyJul 18, 16Nov 10, 16[H01L]
2016/0329,294 BALL BONDING METAL WIRE BOND WIRES TO METAL PADSJul 10, 15Nov 10, 16[H01L]
2016/0329,300 NEW 2.5D MICROELECTRONIC ASSEMBLY AND METHOD WITH CIRCUIT STRUCTURE FORMED ON CARRIERMay 05, 16Nov 10, 16[H01L]
2016/0329,301 METHOD FOR PREPARING LOW COST SUBSTRATESMay 25, 16Nov 10, 16[C25F, H01L]
2016/0329,308 WIRE BOND SUPPORT STRUCTURE AND MICROELECTRONIC PACKAGE INCLUDING WIRE BONDS THEREFROMJul 22, 16Nov 10, 16[H01L]
2016/0329,309 SSI PoPDec 03, 15Nov 10, 16[H01L]
2016/0322,325 COUPLING OF SIDE SURFACE CONTACTS TO A CIRCUIT PLATFORMApr 28, 15Nov 03, 16[B81C, B23K, B81B, H01L]
2016/0322,456 MAKING MULTILAYER 3D CAPACITORS USING ARRAYS OF UPSTANDING RODS OR RIDGESJul 12, 16Nov 03, 16[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,508,629 Memory module in a packageFeb 22, 16Nov 29, 16[G11C, H01L]
9,508,638 Making electrical components in handle wafers of integrated circuit packagesAug 24, 15Nov 29, 16[H01L]
9,508,689 Electrical connector between die pad and z-interconnect for stacked die assembliesSep 30, 15Nov 29, 16[H01L]
9,508,691 Flipped die stacks with multiple rows of leadframe interconnectsDec 16, 15Nov 29, 16[H01L]
9,502,347 Microelectronic assemblies formed using metal silicide, and methods of fabricationFeb 23, 15Nov 22, 16[H01L]
9,502,372 Wafer-level packaging using wire bond wires in place of a redistribution layerApr 30, 15Nov 22, 16[H01L]
9,502,390 BVA interposerMar 12, 13Nov 22, 16[H01L, H05K]
9,496,154 Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate viasSep 16, 14Nov 15, 16[H01L]
9,496,242 Stackable microelectronic package structuresMar 16, 15Nov 15, 16[B81C, H01L]
9,496,243 Microelectronic assembly with opposing microelectronic packages each having terminals with signal assignments that mirror each other with respect to a central axisMar 14, 16Nov 15, 16[G11C, H01L]
9,490,195 Wafer-level flipped die stacks with leadframes or metal foil interconnectsOct 15, 15Nov 08, 16[H01L]
9,490,222 Wire bond wires for interference shieldingOct 12, 15Nov 08, 16[H01L]
9,490,230 Selective die electrical insulation by additive processSep 28, 15Nov 08, 16[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
9,117,827 Making electrical components in handle wafers of integrated circuit packagesWithdrawnMay 02, 14Aug 25, 15[H01L]
2014/0008,676 OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICESABANJul 03, 12Jan 09, 14[H01L]
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEABANMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERABANMar 12, 13Jul 25, 13[H01L]
2013/0119,012 INTERCONNECTION ELEMENT FOR ELECTRIC CIRCUITSABANOct 26, 12May 16, 13[H01R]
2013/0119,117 BONDING WEDGEABANNov 02, 12May 16, 13[H01L]
2013/0070,437 HYBRID INTERPOSERABANSep 20, 11Mar 21, 13[H01R, H05K]
2013/0068,516 HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIASABANSep 19, 11Mar 21, 13[H05K]
2013/0037,312 HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATIONABANAug 10, 11Feb 14, 13[B05D, B32B, H05K]
8,119,516 Bump structure formed from using removable mandrelExpiredNov 04, 08Feb 21, 12[H01L]
8,112,881 Method for manufacturing multilayer wiring boardExpiredSep 29, 05Feb 14, 12[H05K]
2011/0197,655 MULTI-LAYERED CERAMIC MICRO-GAS CHROMATOGRAPH AND METHOD FOR MAKING THE SAMEABANDec 07, 10Aug 18, 11[G01N]
7,856,444 Performing a search using a search parameterExpiredDec 27, 04Dec 21, 10[G06F]
7,843,046 Flat leadless packages and stacked leadless package assembliesExpiredAug 27, 08Nov 30, 10[H01L]
2010/0242,270 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit moduleABANFeb 16, 10Sep 30, 10[H01K]
2010/0071,944 CHIP CAPACITOR EMBEDDED PWBABANDec 17, 07Mar 25, 10[H05K]
2010/0044,860 Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layerABANJul 30, 09Feb 25, 10[H01L]
2009/0106,488 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKSABANOct 20, 08Apr 23, 09[G06F]
2009/0071,707 Multilayer substrate with interconnection vias and method of manufacturing the sameABANAug 13, 08Mar 19, 09[H05K, C25D]
2008/0296,254 Multilayer wiring board for an electronic deviceABANJan 11, 08Dec 04, 08[C23F]

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