INVENSAS CORPORATION

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 53183
 
 
 
G11C STATIC STORES 9868
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 7475
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 36376
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2461
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1135
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 10146
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 10120
 
 
 
H03K PULSE TECHNIQUE 7118
 
 
 
H01K ELECTRIC INCANDESCENT LAMPS 615

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0204,091 INVERTED OPTICAL DEVICEMar 21, 16Jul 14, 16[H01L]
2016/0197,026 Thermal vias disposed in a substrate without a liner layerMar 10, 16Jul 07, 16[H01L]
2016/0189,765 Retention optimized memory device using predictive data inversionMar 09, 16Jun 30, 16[G11C]
2016/0190,100 STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATEMar 03, 16Jun 30, 16[H01L]
2016/0192,496 CONTACT STRUCTURES WITH POROUS NETWORKS FOR SOLDER CONNECTIONS, AND METHODS OF FABRICATING SAMENov 16, 15Jun 30, 16[H05K]
2016/0172,268 Bond Via Array for Thermal ConductivityDec 11, 14Jun 16, 16[H01L]
2016/0172,319 COMPACT SEMICONDUCTOR PACKAGE AND RELATED METHODSFeb 08, 16Jun 16, 16[H01L]
2016/0172,332 MEMORY MODULE IN A PACKAGEFeb 22, 16Jun 16, 16[H01L]
2016/0172,402 IMAGE SENSOR DEVICENov 18, 15Jun 16, 16[H01L]
2016/0163,639 Substrate-less Stackable Package with Wire-Bond InterconnectFeb 11, 16Jun 09, 16[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,397,038 Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substratesFeb 27, 15Jul 19, 16[H01L]
9,397,051 Warpage reduction in structures with electrical circuitryDec 03, 13Jul 19, 16[H01L]
9,398,700 Method of forming a reliable microelectronic assemblyJun 21, 13Jul 19, 16[H01L, H05K]
9,390,998 Heat spreading substrateFeb 17, 12Jul 12, 16[H01L]
9,391,008 Reconstituted wafer-level package DRAMJul 31, 12Jul 12, 16[H01L]
9,385,036 Reliable packaging and interconnect structuresJul 11, 14Jul 05, 16[H01L]
9,377,824 Microelectronic assembly including memory packages connected to circuit panel, the memory packages having stub minimization for wirebond assemblies without windowsApr 03, 14Jun 28, 16[G06F, H01L, H05K]
9,378,985 Method of thinning a wafer to provide a raised peripheral edgeJul 23, 15Jun 28, 16[H01L]
9,379,008 Metal PVD-free conducting structuresFeb 20, 15Jun 28, 16[H01L]
9,379,074 Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnectsApr 10, 14Jun 28, 16[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
9,117,827 Making electrical components in handle wafers of integrated circuit packagesWithdrawnMay 02, 14Aug 25, 15[H01L]
2014/0008,676 OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICESABANJul 03, 12Jan 09, 14[H01L]
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEABANMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERABANMar 12, 13Jul 25, 13[H01L]
2013/0119,012 INTERCONNECTION ELEMENT FOR ELECTRIC CIRCUITSABANOct 26, 12May 16, 13[H01R]
2013/0119,117 BONDING WEDGEABANNov 02, 12May 16, 13[H01L]
2013/0070,437 HYBRID INTERPOSERABANSep 20, 11Mar 21, 13[H01R, H05K]
2013/0068,516 HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIASABANSep 19, 11Mar 21, 13[H05K]
2013/0037,312 HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATIONABANAug 10, 11Feb 14, 13[B05D, B32B, H05K]
8,119,516 Bump structure formed from using removable mandrelExpiredNov 04, 08Feb 21, 12[H01L]
8,112,881 Method for manufacturing multilayer wiring boardExpiredSep 29, 05Feb 14, 12[H05K]
2011/0197,655 MULTI-LAYERED CERAMIC MICRO-GAS CHROMATOGRAPH AND METHOD FOR MAKING THE SAMEABANDec 07, 10Aug 18, 11[G01N]
7,856,444 Performing a search using a search parameterExpiredDec 27, 04Dec 21, 10[G06F]
7,843,046 Flat leadless packages and stacked leadless package assembliesExpiredAug 27, 08Nov 30, 10[H01L]
2010/0242,270 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit moduleABANFeb 16, 10Sep 30, 10[H01K]
2010/0071,944 CHIP CAPACITOR EMBEDDED PWBABANDec 17, 07Mar 25, 10[H05K]
2010/0044,860 Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layerABANJul 30, 09Feb 25, 10[H01L]
2009/0106,488 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKSABANOct 20, 08Apr 23, 09[G06F]
2009/0071,707 Multilayer substrate with interconnection vias and method of manufacturing the sameABANAug 13, 08Mar 19, 09[H05K, C25D]
2008/0296,254 Multilayer wiring board for an electronic deviceABANJan 11, 08Dec 04, 08[C23F]

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