INVENSAS CORPORATION

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 40688
 
 
 
G11C STATIC STORES 8368
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 6376
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 36357
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2259
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 13105
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1130
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 9126
 
 
 
B05D PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL 690
 
 
 
H01K ELECTRIC INCANDESCENT LAMPS 616

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0332,980 METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICESMay 12, 14Nov 13, 14[H01L]
2014/0328,015 STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWSApr 03, 14Nov 06, 14[G06F]
2014/0328,016 STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWSApr 03, 14Nov 06, 14[G06F]
2014/0313,834 RETENTION OPTIMIZED MEMORY DEVICE USING PREDICTIVE DATA INVERSIONApr 23, 13Oct 23, 14[G11C]
2014/0315,384 METHOD OF PROCESSING A DEVICE SUBSTRATEJul 03, 14Oct 23, 14[H01L]
2014/0262,457 POROUS ALUMINA TEMPLATES FOR ELECTRONIC PACKAGESMar 12, 13Sep 18, 14[H05K]
2014/0263,582 LOW COST INTERPOSER AND METHOD OF FABRICATIONMar 14, 13Sep 18, 14[H01L]
2014/0264,730 MICROELECTRONIC ELEMENTS WITH MASTER/SLAVE CONFIGURABILITYMar 13, 13Sep 18, 14[H01L]
2014/0264,794 LOW CTE INTERPOSER WITHOUT TSV STRUCTUREMar 14, 13Sep 18, 14[H01L, H05K]
2014/0268,491 CAPACITORS USING POROUS ALUMINA STRUCTURESMar 12, 13Sep 18, 14[H01G]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,883,563 Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulationMar 31, 14Nov 11, 14[H01L]
8,884,403 Semiconductor die array structureDec 30, 10Nov 11, 14[H01L]
8,884,427 Low CTE interposer without TSV structureMar 14, 13Nov 11, 14[H01L, H05K]
8,878,353 Structure for microelectronic packaging with bond elements to encapsulation surfaceDec 20, 12Nov 04, 14[H01L, H05K]
8,873,302 Common doped region with separate gate control for a logic compatible non-volatile memory cellOct 28, 11Oct 28, 14[G11C, H01L]
8,865,570 Chips with high fracture toughness through a metal ringJan 02, 14Oct 21, 14[H01L]
8,859,420 Structure and method of making interconnect element, and multilayer wiring board including the interconnect elementApr 12, 11Oct 14, 14[H01L, H05K]
8,846,447 Thin wafer handling and known good die test methodAug 23, 12Sep 30, 14[G01R, H01L]
8,847,412 Microelectronic assembly with thermally and electrically conductive underfillNov 09, 12Sep 30, 14[H01L]
8,848,391 Co-support component and microelectronic assemblyMar 15, 13Sep 30, 14[H05K]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERMar 12, 13Jul 25, 13[H01L]
2013/0119,117 BONDING WEDGENov 02, 12May 16, 13[H01L]
2011/0197,655 MULTI-LAYERED CERAMIC MICRO-GAS CHROMATOGRAPH AND METHOD FOR MAKING THE SAMEDec 07, 10Aug 18, 11[G01N]
2010/0242,270 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit moduleFeb 16, 10Sep 30, 10[H01K]
2010/0071,944 CHIP CAPACITOR EMBEDDED PWBDec 17, 07Mar 25, 10[H05K]
2009/0106,488 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKSOct 20, 08Apr 23, 09[G06F]
2009/0071,707 Multilayer substrate with interconnection vias and method of manufacturing the sameAug 13, 08Mar 19, 09[H05K, C25D]
2008/0296,254 Multilayer wiring board for an electronic deviceJan 11, 08Dec 04, 08[C23F]
2008/0264,678 Member for Interconnecting Wiring Films and Method for Producing the SameSep 06, 05Oct 30, 08[H05K]
2008/0169,568 Structure and method of making interconnect element having metal traces embedded in surface of dielectricAug 29, 07Jul 17, 08[H01L]
2008/0136,041 Structure and method of making interconnect element having metal traces embedded in surface of dielectricMay 23, 07Jun 12, 08[H01L]
2008/0128,288 Method of manufacturing a multi-layer wiring board using a metal member having a rough surfaceJun 08, 07Jun 05, 08[C25D]
2007/0221,329 Apparatus and method for distributing a liquid onto a surface of an itemOct 23, 06Sep 27, 07[B44C, H01L]
2007/0069,377 CLOCK DISTRIBUTION NETWORKS AND CONDUCTIVE LINES IN SEMICONDUCTOR INTEGRATED CIRCUITSNov 14, 06Mar 29, 07[H01L]
7,144,056 Detection and handling of semiconductor wafers and wafers-like objectsMar 25, 03Dec 05, 06[B25J]
2006/0076,661 Attachment of integrated circuit structures and other substrates to substrates with viasOct 19, 05Apr 13, 06[H01L]
7,027,894 Article holders with sensors detecting a type of article held by the holderSep 09, 03Apr 11, 06[G05B]
2005/0224,256 Interlayer member used for producing multilayer wiring board and method of producing the sameMar 22, 05Oct 13, 05[H01L, H05K]
2005/0212,127 Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavitiesMay 24, 05Sep 29, 05[H01L]

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