INVENSAS CORPORATION

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 41889
 
 
 
G11C STATIC STORES 8471
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 6275
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 35353
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2257
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1229
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 12109
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 9136
 
 
 
H01K ELECTRIC INCANDESCENT LAMPS 617
 
 
 
H03K PULSE TECHNIQUE 6120

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0014,688 Thin Wafer Handling and Known Good Die Test MethodSep 29, 14Jan 15, 15[H01L]
2015/0014,847 MICROELECTRONIC ASSEMBLIES WITH STACK TERMINALS COUPLED BY CONNECTORS EXTENDING THROUGH ENCAPSULATIONJul 15, 13Jan 15, 15[H01L]
2015/0014,856 MICROELECTRONIC ASSEMBLIES HAVING REINFORCING COLLARS ON CONNECTORS EXTENDING THROUGH ENCAPSULATIONJul 15, 13Jan 15, 15[H01L]
2015/0017,763 Microelectronic Assembly With Thermally and Electrically Conductive UnderfillSep 29, 14Jan 15, 15[H01L]
2015/0017,765 METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACEFeb 14, 13Jan 15, 15[H01L]
2014/0376,200 RELIABLE DEVICE ASSEMBLYJun 21, 13Dec 25, 14[H05K]
2014/0367,866 MEMORY MODULE IN A PACKAGEAug 29, 14Dec 18, 14[H01L]
2014/0362,629 SINGLE PACKAGE DUAL CHANNEL MEMORY WITH CO-SUPPORTNov 08, 13Dec 11, 14[G11C]
2014/0346,646 STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERSAug 11, 14Nov 27, 14[H01L]
2014/0339,702 METAL PVD-FREE CONDUCTING STRUCTURESMay 20, 13Nov 20, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,916,781 Cavities containing multi-wiring structures and devicesNov 15, 11Dec 23, 14[H01R, H01L, H05K]
8,917,532 Stub minimization with terminal grids offset from center of packageOct 03, 12Dec 23, 14[G11C, H01L, H05K]
8,912,024 Front facing piggyback wafer assemblyNov 18, 11Dec 16, 14[F21K, F21Y, H01L]
8,912,661 Stacked die assembly having reduced stress electrical interconnectsNov 04, 10Dec 16, 14[H01L]
8,907,500 Multi-die wirebond packages with elongated windowsFeb 04, 13Dec 09, 14[H01L]
8,900,464 Method of making a microelectronic interconnect element with decreased conductor spacingJun 10, 13Dec 02, 14[B44C, H01B, B81C, H01L, C25D]
8,900,910 Rear-face illuminated solid state image sensorsJan 06, 14Dec 02, 14[H01L]
8,900,974 High yield substrate assemblyMay 02, 12Dec 02, 14[H01L]
8,890,304 Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer materialJun 08, 11Nov 18, 14[H01L]
8,883,563 Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulationMar 31, 14Nov 11, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERMar 12, 13Jul 25, 13[H01L]
2013/0119,117 BONDING WEDGENov 02, 12May 16, 13[H01L]
2013/0070,437 HYBRID INTERPOSERSep 20, 11Mar 21, 13[H01R, H05K]
2013/0068,516 HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIASSep 19, 11Mar 21, 13[H05K]
2013/0037,312 HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATIONAug 10, 11Feb 14, 13[B05D, B32B, H05K]
2011/0197,655 MULTI-LAYERED CERAMIC MICRO-GAS CHROMATOGRAPH AND METHOD FOR MAKING THE SAMEDec 07, 10Aug 18, 11[G01N]
7,856,444 Performing a search using a search parameterDec 27, 04Dec 21, 10[G06F]
7,843,046 Flat leadless packages and stacked leadless package assembliesAug 27, 08Nov 30, 10[H01L]
2010/0242,270 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit moduleFeb 16, 10Sep 30, 10[H01K]
2010/0071,944 CHIP CAPACITOR EMBEDDED PWBDec 17, 07Mar 25, 10[H05K]
2009/0106,488 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKSOct 20, 08Apr 23, 09[G06F]
2009/0071,707 Multilayer substrate with interconnection vias and method of manufacturing the sameAug 13, 08Mar 19, 09[H05K, C25D]
2008/0296,254 Multilayer wiring board for an electronic deviceJan 11, 08Dec 04, 08[C23F]
2008/0264,678 Member for Interconnecting Wiring Films and Method for Producing the SameSep 06, 05Oct 30, 08[H05K]
2008/0169,568 Structure and method of making interconnect element having metal traces embedded in surface of dielectricAug 29, 07Jul 17, 08[H01L]
2008/0136,041 Structure and method of making interconnect element having metal traces embedded in surface of dielectricMay 23, 07Jun 12, 08[H01L]
2008/0128,288 Method of manufacturing a multi-layer wiring board using a metal member having a rough surfaceJun 08, 07Jun 05, 08[C25D]
2007/0221,329 Apparatus and method for distributing a liquid onto a surface of an itemOct 23, 06Sep 27, 07[B44C, H01L]
2007/0069,377 CLOCK DISTRIBUTION NETWORKS AND CONDUCTIVE LINES IN SEMICONDUCTOR INTEGRATED CIRCUITSNov 14, 06Mar 29, 07[H01L]

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