INVENSAS CORPORATION

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 49384
 
 
 
G11C STATIC STORES 9168
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 7372
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 36372
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 2460
 
 
 
C25D PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING 1130
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 11113
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 10137
 
 
 
H01K ELECTRIC INCANDESCENT LAMPS 717
 
 
 
H03K PULSE TECHNIQUE 6121

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0027,761 ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIESSep 30, 15Jan 28, 16[H01L]
2016/0020,121 EMBEDDED PACKAGING WITH PREFORMED VIASSep 30, 15Jan 21, 16[H01L]
2016/0020,188 SELECTIVE DIE ELECTRICAL INSULATION BY ADDITIVE PROCESSSep 28, 15Jan 21, 16[H01L]
2015/0380,375 MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS AND STIFFENING LAYERSep 10, 15Dec 31, 15[H01L]
2015/0380,377 Multiple bond via arrays of different wire heights on a same substrateAug 31, 15Dec 31, 15[H01L]
2015/0371,938 BACK-END-OF-LINE STACK FOR A STACKED DEVICEJun 19, 14Dec 24, 15[H01L]
2015/0371,968 MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURESAug 27, 15Dec 24, 15[H01L]
2015/0364,450 CO-SUPPORT FOR XFD PACKAGINGAug 27, 15Dec 17, 15[H01L]
2015/0364,457 Wafer Leveled Chip Packaging Structure and Method ThereofJun 15, 15Dec 17, 15[H01L]
2015/0364,538 MAKING MULTILAYER 3D CAPACITORS USING ARRAYS OF UPSTANDING RODS OR RIDGESJun 13, 14Dec 17, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,252,116 Semiconductor die mount by conformal die coatingApr 01, 14Feb 02, 16[H01L]
9,252,122 Package-on-package assembly with wire bond viasAug 14, 13Feb 02, 16[H01L, H05K]
9,252,127 Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufactureJul 10, 14Feb 02, 16[H01L]
9,241,420 In-package fly-by signalingMay 12, 14Jan 19, 16[G11C, H01L, H05K]
9,236,365 Methods of forming 3-D circuits with integrated passive devicesMay 12, 14Jan 12, 16[H01L]
9,237,648 Carrier-less silicon interposerFeb 25, 13Jan 12, 16[H01L, H05K]
9,230,814 Non-volatile memory devices having vertical drain to gate capacitive couplingOct 28, 11Jan 05, 16[G11C, H01L]
9,224,431 Stub minimization using duplicate sets of signal terminalsMar 06, 14Dec 29, 15[G11C, H01L]
9,224,739 Method of making integrated circuit embedded with non-volatile programmable memory having variable couplingOct 08, 13Dec 29, 15[G11C, H01L]
9,226,396 Porous alumina templates for electronic packagesMar 12, 13Dec 29, 15[H01L, H05K]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
9,117,827 Making electrical components in handle wafers of integrated circuit packagesWithdrawnMay 02, 14Aug 25, 15[H01L]
2014/0008,676 OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICESABANJul 03, 12Jan 09, 14[H01L]
2013/0247,372 MULTILAYER WIRING BOARD FOR AN ELECTRONIC DEVICEABANMay 17, 13Sep 26, 13[H05K]
2013/0186,944 MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYERABANMar 12, 13Jul 25, 13[H01L]
2013/0119,012 INTERCONNECTION ELEMENT FOR ELECTRIC CIRCUITSABANOct 26, 12May 16, 13[H01R]
2013/0119,117 BONDING WEDGEABANNov 02, 12May 16, 13[H01L]
2013/0070,437 HYBRID INTERPOSERABANSep 20, 11Mar 21, 13[H01R, H05K]
2013/0068,516 HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIASABANSep 19, 11Mar 21, 13[H05K]
2013/0037,312 HIGH DENSITY TRACE FORMATION METHOD BY LASER ABLATIONABANAug 10, 11Feb 14, 13[B05D, B32B, H05K]
2011/0197,655 MULTI-LAYERED CERAMIC MICRO-GAS CHROMATOGRAPH AND METHOD FOR MAKING THE SAMEABANDec 07, 10Aug 18, 11[G01N]
7,856,444 Performing a search using a search parameterExpiredDec 27, 04Dec 21, 10[G06F]
7,843,046 Flat leadless packages and stacked leadless package assembliesExpiredAug 27, 08Nov 30, 10[H01L]
2010/0242,270 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit moduleABANFeb 16, 10Sep 30, 10[H01K]
2010/0071,944 CHIP CAPACITOR EMBEDDED PWBABANDec 17, 07Mar 25, 10[H05K]
2010/0044,860 Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layerABANJul 30, 09Feb 25, 10[H01L]
2009/0106,488 STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKSABANOct 20, 08Apr 23, 09[G06F]
2009/0071,707 Multilayer substrate with interconnection vias and method of manufacturing the sameABANAug 13, 08Mar 19, 09[H05K, C25D]
2008/0296,254 Multilayer wiring board for an electronic deviceABANJan 11, 08Dec 04, 08[C23F]
2008/0264,678 Member for Interconnecting Wiring Films and Method for Producing the SameABANSep 06, 05Oct 30, 08[H05K]
2008/0169,568 Structure and method of making interconnect element having metal traces embedded in surface of dielectricABANAug 29, 07Jul 17, 08[H01L]

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