LATTICE SEMICONDUCTOR CORPORATION

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H03K PULSE TECHNIQUE 25716
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 106260
 
 
 
G11C STATIC STORES 8070
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 66241
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 22115
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2281
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 1950
 
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 1279
 
 
 
H03B GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS 944
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 8189

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0136,914 HIGHLY SECURE AND EXTENSIVE SCAN TESTING OF INTEGRATED CIRCUITSApr 08, 13May 15, 14[G01R]
2014/0104,934 Leakage-Current Abatement Circuity for Memory ArraysFeb 26, 13Apr 17, 14[G11C]
2014/0105,265 LOSS OF SIGNAL DETECTION FOR HIGH-SPEED SERIAL LINKSApr 23, 13Apr 17, 14[H04L]
2014/0108,628 CONFIGURATION SEQUENCE FOR PROGRAMMABLE LOGIC DEVICEMay 29, 13Apr 17, 14[H04L]
2014/0109,031 CONFIGURATION OF SELECTED MODULES OF A HARDWARE BLOCK WITHIN A PROGRAMMABLE LOGIC DEVICEOct 14, 13Apr 17, 14[G06F]
2014/0009,194 PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHSSep 09, 13Jan 09, 14[H03L]
2013/0258,761 DUAL-PORT SRAM WITH BIT LINE CLAMPINGMay 24, 13Oct 03, 13[G11C]
2013/0249,717 Delaying Data SignalsMay 13, 13Sep 26, 13[H03K, H03M]
2010/0301,898 FPGA HAVING LOW POWER, FAST CARRY CHAINJun 01, 09Dec 02, 10[H03K]
2010/0079,166 Programmable Signal Routing Systems Having Low Static LeakageSep 26, 08Apr 01, 10[H03K]

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,786,482 Integrated circuit with pin for setting digital addressApr 05, 13Jul 22, 14[H03M]
8,710,898 Triple-trim reference voltage generatorOct 17, 12Apr 29, 14[H03F, G06G]
8,686,773 In-system margin measurement circuitDec 20, 12Apr 01, 14[H03K]
8,664,774 Bondwire configuration for reduced crosstalkApr 09, 10Mar 04, 14[H01L]
8,654,600 Low-voltage current sense amplifierMar 01, 11Feb 18, 14[G11C]
8,648,636 Delaying data signalsMay 13, 13Feb 11, 14[H03L]
8,643,168 Integrated circuit package with input capacitance compensationNov 26, 12Feb 04, 14[H01L]
8,643,398 Placing integrated circuits into low voltage mode for standby purposesNov 19, 12Feb 04, 14[H03K]
8,553,463 Voltage discharge circuit having divided discharge currentMar 21, 11Oct 08, 13[G11C]
8,555,217 Integrated circuit design software with cross probing between tool graphical user interfaces (GUIs)Jun 20, 11Oct 08, 13[G06T, G06F]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2009/0037,160 METHOD AND APPARATUS TO SERVE IBIS DATAJul 31, 07Feb 05, 09[G06F]
2008/0028,521 Formation of high voltage transistor with high breakdown voltageJul 17, 06Feb 07, 08[A47G]
2007/0267,715 Shallow trench isolation (STI) with trench liner of increased thicknessMay 18, 06Nov 22, 07[H01L]
2007/0200,196 Shallow trench isolation (STI) devices and processesFeb 24, 06Aug 30, 07[H01L]
2007/0182,495 Oscillator systems and methodsFeb 09, 06Aug 09, 07[H03L]
2007/0121,711 PLL with programmable jitter for loopback serdes testing and the likeNov 30, 05May 31, 07[H04L]
2007/0111,403 Polycide fuse with reduced programming timeNov 15, 05May 17, 07[H01L]
2007/0030,736 Variable source resistor for flash memoryAug 03, 05Feb 08, 07[G11C]
2007/0033,507 Efficient error code correctionAug 03, 05Feb 08, 07[H03M]
2006/0261,882 Bandgap generator providing low-voltage operationMay 17, 05Nov 23, 06[G05F]
2006/0202,306 Bipolar junction transistor with high betaMar 11, 05Sep 14, 06[H01L]
2006/0157,748 Metal junction diode and processJan 20, 05Jul 20, 06[H01L]
2006/0145,238 Diode structure for word-line protection in a memory circuitJan 05, 05Jul 06, 06[H01L]
2006/0125,014 Diode with low junction capacitanceDec 14, 04Jun 15, 06[H01L]
2006/0128,162 Process for fabricating a semiconductor device having an RTCVD layerDec 14, 04Jun 15, 06[H01L]
6,977,408 High-performance non-volatile memory device and fabrication processJun 30, 03Dec 20, 05[H01L]
6,976,047 Skipped carry incrementer for FFT address generationMar 28, 02Dec 13, 05[G06F]
2005/0252,504 Collapsible cooking standMay 11, 05Nov 17, 05[F24C]
2005/0213,271 Electrostatic discharge protection circuitsMar 24, 04Sep 29, 05[H02H]
6,907,439 FFT address generation method and apparatusMar 26, 02Jun 14, 05[G06F]

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