LATTICE SEMICONDUCTOR CORPORATION

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Technologies

Intl Class Technology # of Patents Rank
 
 
 
H03K PULSE TECHNIQUE 25914
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 102202
 
 
 
G11C STATIC STORES 7668
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 74183
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2274
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 21107
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 1654
 
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 1174
 
 
 
H03B GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS 942
 
 
 
H04B TRANSMISSION 7157

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,892,962 FPGA-based processorNov 12, 96Apr 06, 99[G06F]196
5,835,405 Application specific modules in a programmable logic deviceApr 10, 97Nov 10, 98[G11C]144
6,284,626 Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trenchApr 06, 99Sep 04, 01[H01L]131
5,559,450 Field programmable gate array with multi-port RAMJul 27, 95Sep 24, 96[H03K]128
7,028,281 FPGA with register-intensive architectureJul 12, 02Apr 11, 06[G06F]120
6,020,755 Hybrid programmable gate arraysSep 26, 97Feb 01, 00[H03K]118
6,275,064 Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuitsDec 22, 97Aug 14, 01[G06F, H03K]112
6,034,538 Virtual logic system for reconfigurable hardwareJan 21, 98Mar 07, 00[G06F, H03K]112
6,163,168 Efficient interconnect network for use in FPGA device having variable grain architectureDec 09, 98Dec 19, 00[H01L, H03K]111
6,348,813 Scalable architecture for high density CPLD's having two-level hierarchy of routing resourcesNov 22, 00Feb 19, 02[H03K]109

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2010/0301,898 FPGA HAVING LOW POWER, FAST CARRY CHAINJun 01, 09Dec 02, 10[H03K]
2010/0079,166 Programmable Signal Routing Systems Having Low Static LeakageSep 26, 08Apr 01, 10[H03K]
2009/0037,160 METHOD AND APPARATUS TO SERVE IBIS DATAJul 31, 07Feb 05, 09[G06F]
2008/0204,073 REDUNDANT CONFIGURATION MEMORY SYSTEMS AND METHODSFeb 28, 07Aug 28, 08[H03K]
2008/0028,521 Formation of high voltage transistor with high breakdown voltageJul 17, 06Feb 07, 08[A47G]
2008/0024,171 Switch sequencing circuit systems and methodsJul 28, 06Jan 31, 08[H03K]
2008/0019,504 Key Generation For Advanced Encryption Standard (AES) Decryption And The LikeJun 20, 06Jan 24, 08[H04L]
2007/0267,715 Shallow trench isolation (STI) with trench liner of increased thicknessMay 18, 06Nov 22, 07[H01L]
2007/0200,196 Shallow trench isolation (STI) devices and processesFeb 24, 06Aug 30, 07[H01L]
2007/0201,543 Dynamic phase offset measurementFeb 24, 06Aug 30, 07[H04B]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,384,427 Configuring multiple programmable logic devices with serial peripheral interfacesApr 01, 10Feb 26, 13[G11C, H03K]
8,384,428 Pre-configuration programmability of I/O circuitryJan 14, 11Feb 26, 13[H01L, H03K]
8,368,424 Programmable logic device wakeup using a general purpose input/output portMar 01, 11Feb 05, 13[H03K]
8,370,691 Testing of soft error detection logic for programmable logic devicesNov 18, 11Feb 05, 13[G01R, G11C, G06F]
8,351,287 Bitline floating circuit for memory power reductionDec 22, 10Jan 08, 13[G11C]
8,324,934 Programmable bufferJan 17, 11Dec 04, 12[H03K]
8,319,521 Safe programming of key information into non-volatile memory for a programmable logic deviceMar 30, 11Nov 27, 12[H01L, H03K]
8,314,632 Method and system for placing integrated circuits into predominantly ultra-low voltage mode for standby purposesJul 29, 11Nov 20, 12[H03K]
8,314,634 Power control block with output glitch protectionApr 04, 11Nov 20, 12[H03K]
8,286,116 Composite wire indexing for programmable logic devicesAug 30, 10Oct 09, 12[G06F]

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Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
Agrawal Om P
San Jose, CA
126
Sharpe-Geisler Bradley A
San Jose, CA
89
Mehta Sunil D
San Jose, CA
55
Shen Ju
San Jose, CA
50
Singh Satwant
Fremont, CA
33
Andrews William B
Emmaus, PA
32
Tang Howard
San Jose, CA
31
Fontana Fabiano
San Jose, CA
30
Nguyen Bai
San Jose, CA
28
Li Xiao-Yu
San Jose, CA
26