LATTICE SEMICONDUCTOR CORPORATION

Patent Owner

Follow Compare Add to Portfolio 6Status Updates

Stats

Details

Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H03K PULSE TECHNIQUE 30117
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 206240
 
 
 
G11C STATIC STORES 10371
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 93176
 
 
 
H04N PICTORIAL COMMUNICATION, e.g. TELEVISION 78146
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 73270
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 4666
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 38123
 
 
 
H04B TRANSMISSION 36166
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 3446

Top Patents (by citation)

Upgrade to the Premium Level to View Top Patents for this Owner. Learn More

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0041,127 ACOUSTIC GESTURE RECOGNITION SYSTEMS AND METHODSOct 21, 16Feb 09, 17[G01S, H04L]
2017/0029,107 WIRELESS CONTROL OF UNMANNED AERIAL VEHICLE WITH DISTANCE RANGING AND CHANNEL SENSINGJul 29, 16Feb 02, 17[G08G, H04W, B64C, G05D]
2017/0012,624 Crowbar Current EliminationJul 08, 15Jan 12, 17[H03K]
2017/0005,836 Driving Data of Multiple Protocols Through a Single Set Of PinsJul 29, 16Jan 05, 17[H04L, G09G, H03K]
2016/0373,244 PHASE TRACKING FOR CLOCK AND DATA RECOVERYFeb 27, 15Dec 22, 16[H04L, H03L]
2016/0344,645 DELAY SPECIFIC ROUTINGS FOR PROGRAMMABLE LOGIC DEVICESMay 18, 15Nov 24, 16[H04L]
2016/0335,383 AREA-EFFICIENT MEMORY MAPPING TECHNIQUES FOR PROGRAMMABLE LOGIC DEVICESMay 15, 15Nov 17, 16[G06F]
2016/0320,448 Programmable Circuits for Correcting Scan-Test Circuitry Defects in Integrated Circuit DesignsApr 28, 15Nov 03, 16[G01R]
2016/0321,385 CLOCK PLACEMENT FOR PROGRAMMABLE LOGIC DEVICESApr 28, 15Nov 03, 16[G06F]
2016/0295,221 Port Processor Capable of Performing Authentication for Multiple Source DevicesApr 01, 15Oct 06, 16[H04N]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9559694 Stable supply-side reference over extended voltage range with hot-plugging compatibilityJul 22, 13Jan 31, 17[H03K]
9559707 Phase locked loop with sub-harmonic locking prevention functionalityOct 23, 14Jan 31, 17[H03L]
9553634 Electrical duplex to optical conversionDec 08, 14Jan 24, 17[H04B]
9554183 Caching of capabilities information of counterpart device for efficient handshaking operationMay 08, 14Jan 24, 17[H04N, G06F]
9549015 Communication of multimedia data streams over multiple communication lanesApr 15, 14Jan 17, 17[H04N, H04L]
9542993 Leakage-current abatement circuitry for memory arraysOct 19, 15Jan 10, 17[G01R, H04L, G11C, H01L, H03M]
9543950 High speed complementary NMOS LUT logicJan 30, 15Jan 10, 17[H03K]
9535445 Transistor matching for generation of precise current ratiosApr 04, 14Jan 03, 17[G05F]
9537308 ESD protection using shared RC triggerDec 03, 13Jan 03, 17[H02H, H01L]
9537644 Transmitting multiple differential signals over a reduced number of physical channelsFeb 21, 13Jan 03, 17[H04L, G09G]

View all patents..

Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2016/0134,264 META-STABILITY PREVENTION FOR OSCILLATORSABANNov 07, 14May 12, 16[H03K]
2016/0118,987 Level Shifter With Low Static Power DissipationABANOct 28, 14Apr 28, 16[H03K]
9324293 Conversion of multimedia data streams for use by connected devicesWithdrawnAug 04, 11Apr 26, 16[H04N, H04L, G09G]
2016/0091,669 Electrical Connector with Optical ChannelABANSep 30, 14Mar 31, 16[H01R, G02B]
2016/0026,745 CLOCK TO OUT PATH OPTIMIZATIONABANJul 23, 14Jan 28, 16[G06F]
2015/0370,672 TRIGGER DETECTION FOR POST CONFIGURATION TESTING OF PROGRAMMABLE LOGIC DEVICESABANJun 24, 14Dec 24, 15[G06F]
2015/0310,933 Configurable Test Address And Data Generation For Multimode Memory Built-In Self-TestingABANSep 10, 14Oct 29, 15[G11C]
2015/0178,436 CLOCK ASSIGNMENTS FOR PROGRAMMABLE LOGIC DEVICEABANDec 20, 13Jun 25, 15[G06F]
2014/0193,165 ELECTRONIC ALIGNMENT OF OPTICAL SIGNALSABANMar 15, 13Jul 10, 14[H04B]
2014/0168,514 Video Frame SynchronizationABANFeb 19, 14Jun 19, 14[H04N]
2014/0152,891 Method and Apparatus for Reducing Digital Video Image DataABANJan 10, 13Jun 05, 14[H04N]
2014/0009,194 PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHSABANSep 09, 13Jan 09, 14[H03L]
2013/0287,100 MECHANISM FOR FACILITATING COST-EFFICIENT AND LOW-LATENCY ENCODING OF VIDEO STREAMSABANApr 30, 12Oct 31, 13[H04N]
2013/0191,570 MULTI-MEDIA USB DATA TRANSFER OVER DIGITAL INTERACTION INTERFACE FOR VIDEO AND AUDIO (DiiVA)ABANJan 12, 11Jul 25, 13[G06F]
2013/0162,901 RINGING SUPPRESSION IN VIDEO SCALERSABANDec 22, 11Jun 27, 13[H04N]
2012/0158,346 IDDQ TESTING OF CMOS DEVICESABANNov 16, 11Jun 21, 12[G01R, G06F]
2011/0157,473 METHOD, APPARATUS, AND SYSTEM FOR SIMULTANEOUSLY PREVIEWING CONTENTS FROM MULTIPLE PROTECTED SOURCESABANDec 30, 09Jun 30, 11[H04N]
2011/0149,032 TRANSMISSION AND HANDLING OF THREE-DIMENSIONAL VIDEO CONTENTABANDec 13, 10Jun 23, 11[H04N]
2009/0327,572 EXCHANGING INFORMATION BETWEEN COMPONENTS COUPLED WITH AN A I2C BUS VIA SEPARATE BANKSABANJun 30, 08Dec 31, 09[G06F]
2009/0086,695 Mechanism for communication with multiple wireless video area networksABANJun 30, 08Apr 02, 09[H04W]

View all patents..

Top Inventors for This Owner

Upgrade to the Premium Level to View Top Inventors for this Owner. Learn More

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to -1 comparisons!

We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.