LSI LOGIC CORPORATION

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Technologies

Intl Class Technology # of Patents Rank
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 1376 23
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 919 32
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 218 16
 
 
H04N PICTORIAL COMMUNICATION, e.g. TELEVISION 189 51
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 154 53
 
 
G11C STATIC STORES 153 43
 
 
H03K PULSE TECHNIQUE 144 31
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 110 26
 
 
H04B TRANSMISSION 75 92
 
 
G11B INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER 70 71
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Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,399,898 Multi-chip semiconductor arrangements using flip chip dies Nov 12, 92 Mar 21, 95 [H01L, H05K] 343
5,637,920 High contact density ball grid array package for flip-chips Oct 04, 95 Jun 10, 97 [H01L] 246
5,777,360 Hexagonal field programmable gate array architecture Aug 21, 95 Jul 07, 98 [H01L] 238
6,067,262 Redundancy analysis for embedded memories with built-in self test and built-in self repair Dec 11, 98 May 23, 00 [G11C] 235
6,173,374 System and method for peer-to-peer accelerated I/O shipping between host bus adapters in clustered computer network Feb 11, 98 Jan 09, 01 [G06F] 221
5,705,301 Performing optical proximity correction with the aid of design rule checkers Feb 27, 96 Jan 06, 98 [G03F] 211
5,802,287 Single chip universal protocol multi-function ATM network interface Aug 03, 95 Sep 01, 98 [H04L] 205
5,468,681 Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias Jun 15, 94 Nov 21, 95 [H01L] 196
5,822,214 CAD for hexagonal architecture Aug 21, 95 Oct 13, 98 [G06F] 194
5,544,067 Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation Jun 14, 93 Aug 06, 96 [G06F] 190
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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2012/0042,207 METHODS AND STRUCTURES FOR TESTING SAS-2 SPEED OPTIONS IN SPEED NEGOTIATION WINDOWS Mar 26, 07 Feb 16, 12 [G06F]
2011/0274,143 SPREAD SPECTRUM CLOCK SIGNAL GENERATOR METHOD AND SYSTEM May 05, 10 Nov 10, 11 [H03D, H04B]
2011/0246,677 SYSTEMS AND METHODS FOR CONTROLLING COMMANDS FOR TARGET DEVICES Apr 05, 10 Oct 06, 11 [G06F]
2010/0281,297 Firmware recovery in a raid controller by using a dual firmware configuration Apr 29, 09 Nov 04, 10 [G06F]
2010/0247,094 DYNAMIC LOAD BALANCING OF FIBRE CHANNEL TRAFFIC Mar 30, 09 Sep 30, 10 [H04B]
2010/0037,448 ADJUSTABLE EMI BAFFLING APPARATUS FOR DATA STORAGE SYSTEMS Oct 23, 09 Feb 18, 10 [B23P]
2010/0042,966 MULTIPLEXER IMPLEMENTATION Aug 18, 08 Feb 18, 10 [G06F]
2010/0022,060 BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS Oct 06, 09 Jan 28, 10 [H01L]
2009/0323,870 Identification Circuit with Repeatable Output Code Aug 24, 06 Dec 31, 09 [H03D]
2009/0283,904 FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES May 15, 08 Nov 19, 09 [H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,404,960 Method for heat dissipation on semiconductor device Aug 31, 04 Mar 26, 13 [H01L]
8,405,435 Delay locked loop having internal test path Nov 10, 04 Mar 26, 13 [H03L]
8,401,070 Method for robust inverse telecine Nov 10, 05 Mar 19, 13 [H04N]
8,384,165 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Jun 17, 08 Feb 26, 13 [H01L]
8,355,457 Correction-calculation algorithm for estimation of the signal to noise ratio in high bit rate DMT modulation Oct 26, 04 Jan 15, 13 [H04L]
8,350,375 Flipchip bump patterns for efficient I-mesh power distribution schemes May 15, 08 Jan 08, 13 [H01L]
8,315,588 Resistive voltage-down regulator for integrated circuit receivers Apr 30, 04 Nov 20, 12 [H04B]
8,312,499 Tunneling information in compressed audio and/or video bit streams Sep 13, 04 Nov 13, 12 [H04N]
8,260,943 Applying a transfer function to a signal for determining compliance to a specification Dec 29, 05 Sep 04, 12 [G06F]
8,260,982 Method for reducing latency Jun 07, 05 Sep 04, 12 [G06F]

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Top Inventors for This Owner

Inventor Name Address Patent #
Rostoker Michael D
San Jose, US
180
Scepanovic Ranko
San Jose, US
148
Andreev Alexander E
San Jose, US
135
Pasch Nicholas F
Mt. View
112
Koford James S
Mountain View, US
72
Catabay Wilbur G
Saratoga, US
60
Winger Lowell L
Waterloo, US
60
Chia Chok J
Cupertino, US
57
Aronowitz Sheldon
San Jose, US
56
Kapoor Ashok K
Palo Alto, US
56
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