MAGMA DESIGN AUTOMATION, INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 47400
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 2157
 
  
 
G11C STATIC STORES 1150
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 1361
 
  
 
H03K PULSE TECHNIQUE 1130

Top Patents (by citation)

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Recent Publications

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8407650 Method for repeated block modification for chip routingMay 30, 08Mar 26, 13[G06F]
8006216 Dynamic push for topological routing of semiconductor packagesJun 06, 08Aug 23, 11[G06F]
7970590 Parametric timing analysisFeb 22, 08Jun 28, 11[G06F]
7458049 Aggregate sensitivity for statistical static timing analysisJun 12, 06Nov 25, 08[G06F]
7448003 Signal flow driven circuit analysis and partitioning techniqueJun 13, 06Nov 04, 08[G06F]
7434188 Lithographically optimized placement toolMar 09, 06Oct 07, 08[G06F]
7409658 Methods and systems for mixed-mode physical synthesis in electronic design automationJun 01, 05Aug 05, 08[G06F]
7395444 Power status notificationSep 23, 03Jul 01, 08[G06F]
7353488 Flow definition language for designing integrated circuit implementation flowsMay 27, 04Apr 01, 08[G06F]
7346874 Parametric timing analysisJan 31, 05Mar 18, 08[G06F]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
7971168 Method for repeated block timing analysisExpiredMay 29, 08Jun 28, 11[G06F]
2007/0266,359 Relative Floorplanning For Improved Integrated Circuit DesignAbandonedMay 14, 07Nov 15, 07[G06F]
2007/0245,280 SYSTEM AND METHOD FOR PLACEMENT OF SOFT MACROSAbandonedApr 12, 07Oct 18, 07[G06F]
2007/0245,281 Placement-Driven Physical-Hierarchy GenerationAbandonedApr 12, 07Oct 18, 07[G06F]
2007/0136,709 Floorplanning A Hierarchical Physical Design To Improve Placement And RoutingAbandonedDec 08, 06Jun 14, 07[G06F]
2006/0112,357 Sensitivity-current-based model for equivalent waveform propagation in the presence of noise for static timing analysisAbandonedNov 01, 05May 25, 06[G06F]
2006/0053,396 Creating optimized physical implementations from high-level descriptions of electronic design using placement-based informationAbandonedNov 01, 05Mar 09, 06[G06F]
2005/0268,258 Rule-based design consultant and method for integrated circuit designAbandonedJun 01, 05Dec 01, 05[G06F]
2005/0268,269 Methods and systems for cross-probing in integrated circuit designAbandonedJun 01, 05Dec 01, 05[G06F]
6931610 Method for rapid estimation of wire delays and capacitances based on placement of cellsExpiredMay 12, 00Aug 16, 05[G06F]
6904581 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increaseExpiredMay 30, 02Jun 07, 05[G06F]
2005/0117,510 Cell Current ReConstruction Based on Cell Delay and Node Slew RateAbandonedFeb 07, 03Jun 02, 05[H04L]
2005/0066,226 Redundant memory self-testAbandonedSep 23, 03Mar 24, 05[G06F]
6865721 Optimization of the top level in abutted-pin hierarchical physical designExpiredMar 22, 02Mar 08, 05[G06F]
6857116 Optimization of abutted-pin hierarchical physical designExpiredNov 15, 00Feb 15, 05[G06F]
6854093 Facilitating press operation in abutted-pin hierarchical physical designExpiredMar 22, 02Feb 08, 05[G06F]
2004/0153,277 Analytical parasitic constraints generation techniqueAbandonedJan 23, 04Aug 05, 04[G06F]
2004/0153,278 Signal flow driven circuit physical synthesis techniqueAbandonedJan 23, 04Aug 05, 04[G06F]
2004/0148,142 GPS (Global Peak current Searching) Algorithm based on Gate-Level Power AnalysisAbandonedFeb 07, 03Jul 29, 04[G06F]
6757874 Facilitating verification in abutted-pin hierarchical physical designExpiredMar 22, 02Jun 29, 04[G06F]

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