MEARS TECHNOLOGIES, INC.

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Patent Activity in the Last 10 Years

Technologies

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A61B DIAGNOSIS; SURGERY; IDENTIFICATION 1239

Top Patents (by citation)

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
7433729 Infrared biometric finger sensor including infrared antennas and associated methodsSep 03, 04Oct 07, 08[A61B]

Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2011/0215,299 SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND DOPANT DIFFUSION RETARDING IMPLANTS AND RELATED METHODSAbandonedMar 08, 11Sep 08, 11[H01L]
2010/0270,535 ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODSAbandonedMay 18, 10Oct 28, 10[H01L]
2008/0012,004 SPINTRONIC DEVICES WITH CONSTRAINED SPINTRONIC DOPANTAbandonedMar 16, 07Jan 17, 08[H01L]
2007/0187,667 ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICEAbandonedDec 21, 06Aug 16, 07[H01L]
2007/0166,928 METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICEAbandonedDec 21, 06Jul 19, 07[H01L]
2007/0158,640 ELECTRONIC DEVICE INCLUDING A POLED SUPERLATTICE HAVING A NET ELECTRICAL DIPOLE MOMENTAbandonedDec 21, 06Jul 12, 07[H01L]
2007/0063,185 Semiconductor device including a front side strained superlattice layer and a back side stress layerAbandonedSep 25, 06Mar 22, 07[H01L]
2007/0063,186 Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layerAbandonedSep 25, 06Mar 22, 07[H01L]
2007/0020,833 Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer MonolayerAbandonedJul 13, 06Jan 25, 07[H01L]
2007/0020,860 Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related MethodsAbandonedJul 13, 06Jan 25, 07[H01L]
2007/0012,910 Semiconductor Device Including a Channel with a Non-Semiconductor Layer MonolayerAbandonedJul 13, 06Jan 18, 07[H01L]
2007/0015,344 Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress RegionsAbandonedJul 13, 06Jan 18, 07[H01L]
2007/0010,040 Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress LayerAbandonedJul 13, 06Jan 11, 07[H01L]
2006/0289,049 Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor LayerAbandonedJun 30, 06Dec 28, 06[H01L]
2006/0292,765 Method for Making a FINFET Including a SuperlatticeAbandonedJun 28, 06Dec 28, 06[H01L]
2006/0273,299 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A DOPANT BLOCKING SUPERLATTICEAbandonedMay 01, 06Dec 07, 06[H01L]
2006/0267,130 Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice TherebetweenAbandonedJun 20, 06Nov 30, 06[H01L]
2006/0263,980 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNELAbandonedMay 05, 06Nov 23, 06[H01L]
2006/0243,964 METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICEAbandonedMay 05, 06Nov 02, 06[H01L]
2006/0231,857 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A MEMORY CELL WITH A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICEAbandonedMay 30, 06Oct 19, 06[H01L]

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