MICRON TECHNOLOGY, INC.

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Technologies

Intl Class Technology # of Patents Rank
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 8356 1
 
 
G11C STATIC STORES 3228 2
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 1172 25
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 635 3
 
 
H03K PULSE TECHNIQUE 369 9
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 324 2
 
 
C23C COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL 276 3
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 271 12
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 254 11
 
 
H01J ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS 229 15
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Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
6,586,761 Phase change material memory device Sep 07, 01 Jul 01, 03 [H01L] 381
5,128,831 High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias Oct 31, 91 Jul 07, 92 [H05K] 359
6,605,527 Reduced area intersection between electrode and programming element Jun 30, 01 Aug 12, 03 [H01L] 348
5,677,566 Semiconductor chip package May 08, 95 Oct 14, 97 [H01L] 329
5,240,552 Chemical mechanical planarization (CMP) of a semiconductor wafer using acoustical waves for in-situ end point detection Dec 11, 91 Aug 31, 93 [H01L] 320
5,229,647 High density data storage using stacked wafers Sep 21, 92 Jul 20, 93 [H01L] 316
6,020,629 Stacked semiconductor package and method of fabrication Jun 05, 98 Feb 01, 00 [H01L, H05K] 303
5,214,845 Method for producing high speed integrated circuits May 11, 92 Jun 01, 93 [H01L, H05K] 299
5,229,331 Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology Feb 14, 92 Jul 20, 93 [H01L] 280
5,483,741 Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice Nov 07, 94 Jan 16, 96 [H05K] 275
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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0105,755 METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED STRUCTURES Nov 02, 11 May 02, 13 [H01L]
2013/0105,937 SIMPLIFIED PITCH DOUBLING PROCESS FLOW Dec 21, 12 May 02, 13 [H01L]
2013/0105,948 PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS Dec 17, 12 May 02, 13 [H01L]
2013/0105,976 METHOD TO ALIGN MASK PATTERNS Dec 21, 12 May 02, 13 [H01L]
2013/0107,605 PERFORMING FORMING PROCESSES ON RESISTIVE MEMORY Nov 01, 11 May 02, 13 [G11C, H05K]
2013/0107,618 MODIFIED RESET STATE FOR ENHANCED READ MARGIN OF PHASE CHANGE MEMORY Dec 18, 09 May 02, 13 [G11C]
2013/0107,620 METHODS AND APPARATUSES INCLUDING A SELECT TRANSISTOR HAVING A BODY REGION INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL AND/OR AT LEAST A PORTION OF ITS GATE LOCATED IN A SUBSTRATE Oct 26, 11 May 02, 13 [G11C, H01L]
2013/0107,623 MEMORY CELL SENSING Nov 01, 11 May 02, 13 [G11C]
2013/0107,626 METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES Dec 20, 12 May 02, 13 [G11C]
2013/0107,640 APPARATUSES, INTEGRATED CIRCUITS, AND METHODS FOR MEASURING LEAKAGE CURRENT Oct 26, 11 May 02, 13 [G11C]
2013/0109,147 Methods of Forming Metal Oxide and Memory Cells Oct 26, 11 May 02, 13 [C01D, C01G, C01F, H01L, C01B]
2013/0099,189 RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY Nov 30, 12 Apr 25, 13 [H01L]
2013/0099,192 Electronic Devices, Memory Devices and Memory Arrays Dec 11, 12 Apr 25, 13 [H01L]
2013/0099,818 METHODS AND APPARATUSES INCLUDING AN ADJUSTABLE TERMINATION IMPEDANCE RATIO Oct 25, 11 Apr 25, 13 [H03K]
2013/0099,888 Fuses, and Methods of Forming and Using Fuses Oct 19, 11 Apr 25, 13 [H01H]
2013/0102,154 METHODS AND SYSTEMS FOR REMOVING MATERIALS FROM MICROFEATURE WORKPIECES WITH ORGANIC AND/OR NON-AQUEOUS ELECTROLYTIC MEDIA Dec 11, 12 Apr 25, 13 [H01L]
2013/0102,160 Methods of Forming Patterns Dec 11, 12 Apr 25, 13 [G03F, H01L]
2013/0103,863 ALIGNMENT OF INSTRUCTIONS AND REPLIES ACROSS MULTIPLE DEVICES IN A CASCADED SYSTEM, USING BUFFERS OF PROGRAMMABLE DEPTHS Dec 11, 12 Apr 25, 13 [G06F]
2013/0103,890 CALIBRATING MEMORY Oct 25, 11 Apr 25, 13 [G06F]
2013/0103,894 PROGRAMMING A MEMORY DEVICE TO INCREASE DATA RELIABILITY Dec 13, 12 Apr 25, 13 [G06F]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,435,836 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods Jan 14, 11 May 07, 13 [H01L]
8,435,850 Localized compressive strained semiconductor Jul 23, 12 May 07, 13 [H01L]
8,435,859 Methods of forming electrical contacts Feb 16, 11 May 07, 13 [H01L]
8,435,886 Method and system for binding halide-based contaminants Jul 03, 12 May 07, 13 [C23C, H01L]
8,435,889 , methods of forming field effect transistors, and methods of forming conductive contacts Jul 13, 11 May 07, 13 [H01L]
8,435,904 Methods of uniformly removing silicon oxide and an intermediate semiconductor device Aug 04, 10 May 07, 13 [H01L]
8,436,362 Solid state lighting devices with selected thermal expansion and/or surface characteristics, and associated methods Aug 23, 10 May 07, 13 [H01L]
8,436,386 Solid state lighting devices having side reflectivity and associated methods of manufacture Jun 03, 11 May 07, 13 [H01L]
8,436,478 Methods of fluxless micro-piercing of solder balls, and resulting devices Jun 30, 10 May 07, 13 [H01L]
8,436,653 Low power multi-level signaling Sep 07, 11 May 07, 13 [H03K]
8,436,670 Power supply induced signal jitter compensation Jan 13, 11 May 07, 13 [H03H]
8,437,163 Memory dies, stacked memories, memory devices and methods Feb 11, 10 May 07, 13 [G11C]
8,437,174 Memcapacitor devices, field effect transistor devices, non-volatile memory arrays, and methods of programming Feb 15, 10 May 07, 13 [G11C]
8,437,186 Non-volatile memory with both single and multiple level cells Jun 12, 12 May 07, 13 [G11C]
8,437,195 Power-off apparatus, systems, and methods Jan 23, 12 May 07, 13 [G11C]
8,437,198 Method for discharging a voltage from a capacitance in a memory device Aug 27, 12 May 07, 13 [G11C]
8,437,202 I/O circuit with phase mixer for slew rate control Aug 01, 12 May 07, 13 [G11C]
8,437,208 Redundant memory array for replacing memory sections of main memory Mar 26, 12 May 07, 13 [G11C]
8,437,217 Storing operational information in an array of memory cells Jan 24, 11 May 07, 13 [G11C]
8,437,428 Digital frequency locked delay line Nov 17, 11 May 07, 13 [H04L, H04B]
8,437,726 High speed, wide frequency-range, digital phase mixer and methods of operation Mar 04, 11 May 07, 13 [H04B]
8,438,329 System and method for optimizing interconnections of components in a multichip memory module Jan 07, 11 May 07, 13 [G06F]
8,438,345 Multi-priority encoder Jul 01, 11 May 07, 13 [G06F]
8,431,184 Methods of forming electrically conductive structures May 07, 11 Apr 30, 13 [B05D]
8,431,240 Metal plating using seed film Jun 17, 10 Apr 30, 13 [B32B]
8,431,446 Via formation for cross-point memory Dec 29, 09 Apr 30, 13 [H01L]
8,431,456 Methods of forming high density structures and low density structures with a single photomask May 31, 12 Apr 30, 13 [H01L]
8,431,458 Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells Dec 27, 10 Apr 30, 13 [H01L]
8,431,483 Methods of forming electrically conductive plugs and method of forming resistance variable elements Mar 26, 07 Apr 30, 13 [H01L]
8,431,484 Stable electroless fine pitch interconnect plating Apr 04, 11 Apr 30, 13 [H01L]
8,431,923 Semiconductor structure and semiconductor device including a diode structure and methods of forming same Feb 07, 11 Apr 30, 13 [H01L]
8,431,961 Memory devices with a connecting region having a band gap lower than a band gap of a body region Feb 03, 11 Apr 30, 13 [H01L]
8,431,971 Pitch multiplied mask patterns for isolated features Sep 19, 11 Apr 30, 13 [H01L]
8,431,980 Random access memory device utilizing a vertically oriented select transistor Jul 12, 10 Apr 30, 13 [H01L]
8,432,202 Digital locked loops and methods with configurable operating parameters May 30, 12 Apr 30, 13 [H03L]
8,432,738 Apparatus and method for reduced peak power consumption during common operation of multi-nand flash memory devices Mar 03, 10 Apr 30, 13 [G11C]
8,432,743 Method and system for programming non-volatile memory cells based on programming of proximate memory cells Dec 09, 11 Apr 30, 13 [G11C]
8,432,765 Method and apparatus for managing behavior of memory devices Dec 02, 11 Apr 30, 13 [G11C]
8,433,846 Methods and apparatus reading erase block management data in subsets of sectors having user data and control data sections Feb 06, 12 Apr 30, 13 [G06F]

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Top Inventors for This Owner

Inventor Name Address Patent #
Forbes Leonard
Corvallis, US
1220
Sandhu Gurtej S
Boise, US
900
Farnworth Warren M
Nampa, US
698
Akram Salman
Boise, US
672
Ahn Kie Y
Chappaqua, US
644
Forbes Leonard
Corvallis, US
426
Roohparvar Frankie F
Miltitas
381
Wood Alan G
Boise, US
342
Hembree David R
Boise, US
334
Jiang Tongbi
Boise, US
284
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