PATENT BUSINESS DEVELOPMENT, LLC

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Technologies

Intl Class Technology # of Patents Rank
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 12245
 
 
 
F26B DRYING SOLID MATERIALS OR OBJECTS BY REMOVING LIQUID THEREFROM 125
 
 
 
G01B MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS178
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 1127
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 1102

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
6,093,969 Face-to-face (FTF) stacked assembly of substrate-on-bare-chip (SOBC) modulesMay 15, 99Jul 25, 00[H01L]59
6,392,304 Multi-chip memory apparatus and associated methodNov 12, 98May 21, 02[H01L]56
6,002,178 Multiple chip module configuration to simplify testing process and reuse of known-good chip-size package (CSP)Nov 12, 97Dec 14, 99[H01L]44
6,249,052 Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configurationMay 18, 99Jun 19, 01[H01L]41
5,838,072 Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodesFeb 24, 97Nov 17, 98[H01L]40
6,301,121 Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing processApr 05, 99Oct 09, 01[H05K]29
6,369,451 Solder balls and columns with stratified underfills on substrate for flip chip joiningJan 12, 99Apr 09, 02[H01L]17
6,184,092 Self-aligned contact for trench DMOS transistorsNov 23, 99Feb 06, 01[H01L]11
6,677,668 Configuration for testing a substrate mounted with a most performance-demanding integrated circuitNov 28, 00Jan 13, 04[H01L]8
6,165,843 Covered slit isolation between integrated circuit devicesMar 20, 98Dec 26, 00[H01L]7

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2003/0101,615 Apparatus and method for preventing a wafer mapping system of an SMIF system from being polluted by corrosive gases remaining on wafersDec 05, 01Jun 05, 03[F26B]
2003/0014,197 Method and apparatus for wafer analysisJul 13, 01Jan 16, 03[G01B]
2001/0048,158 SOLDER BALLS AND COLUMNS WITH STRATIFIED UNDERFILLS ON SUBSTRATE FOR FLIP CHIP JOININGJan 12, 99Dec 06, 01[B23K, C22C]

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
6,785,617 Method and apparatus for wafer analysisJul 13, 01Aug 31, 04[G01B]
6,677,668 Configuration for testing a substrate mounted with a most performance-demanding integrated circuitNov 28, 00Jan 13, 04[H01L]
6,588,123 Apparatus and method for preventing a wafer mapping system of an SMIF system from being polluted by corrosive gases remaining on wafersDec 05, 01Jul 08, 03[F26B]
6,392,304 Multi-chip memory apparatus and associated methodNov 12, 98May 21, 02[H01L]
6,369,451 Solder balls and columns with stratified underfills on substrate for flip chip joiningJan 12, 99Apr 09, 02[H01L]
6,301,121 Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing processApr 05, 99Oct 09, 01[H05K]
6,265,754 Covered slit isolation between integrated circuit devicesOct 13, 00Jul 24, 01[H01L]
6,249,052 Substrate on chip (SOC) multiple-chip module (MCM) with chip-size-package (CSP) ready configurationMay 18, 99Jun 19, 01[H01L]
6,204,677 Contact pressure jig for signal analysisSep 22, 98Mar 20, 01[G01R]
6,184,092 Self-aligned contact for trench DMOS transistorsNov 23, 99Feb 06, 01[H01L]

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Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
Lin Paul T
673 Hillcrest Ter., Fremont, CA 94539
6
Sung Kuo-Tung
Hsinchu, TW
3
Butler Douglas B
Colorado Springs, CO
1
Chang Su-wen
Hsinchu Shien, TW
1
Chen San Pen
Not Provided
1
Chen Min-Liang
Hsinchu, TW
1
Chen Rong-ching
Taichung Shien, TW
1
Chen San-Pen
Pengtung, TW
1
Hallgren Bruce D
San Jose, CA
1
Li Li-Chun
Los Gatos, CA
1