PDF SOLUTIONS, INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 71291
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 68379
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 9150
 
  
 
H03K PULSE TECHNIQUE 4127
 
  
 
G01N INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES 2204
 
  
 
H01J ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS 2126
 
  
 
G01B MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS198
 
  
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 1103
 
  
 
G06G ANALOGUE COMPUTERS 152
 
  
 
G11C STATIC STORES 1150

Top Patents (by citation)

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Recent Publications

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9922890 Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesSep 30, 17Mar 20, 18[H01L, G06F]
9922968 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cellsMar 31, 17Mar 20, 18[H01L]
9911649 Process for making and using mesh-style NCEM padsSep 08, 16Mar 06, 18[H01L]
9911668 Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesSep 29, 17Mar 06, 18[H01L, G06F]
9911669 Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesSep 29, 17Mar 06, 18[H01L, G06F]
9911670 Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gateSep 30, 17Mar 06, 18[H01L, G06F]
9905487 Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opensSep 28, 16Feb 27, 18[H01L, G06F]
9905553 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cellsDec 27, 16Feb 27, 18[H01L, G06F]
9899276 Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesSep 30, 17Feb 20, 18[H01L, G06F]
9881843 Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gatesSep 29, 17Jan 30, 18[H01L, G06F]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2015/0270,181 OPPORTUNISTIC PLACEMENT OF IC TEST STRUCUTRES AND/OR E-BEAM TARGET PADS IN AREAS OTHERWISE USED FOR FILLER CELLS, TAP CELLS, DECAP CELLS, SCRIBE LINES, AND/OR DUMMY FILL, AS WELL AS PRODUCT IC CHIPS CONTAINING SAMEAbandonedFeb 03, 15Sep 24, 15[H01L, G01R]
8587341 Integrated circuit having high pattern regularityExpiredAug 23, 11Nov 19, 13[H03K]
2011/0213,489 MANUFACTURING OF INTEGRATED CIRCUIT DEVICES USING A GLOBAL PREDICTIVE MONITORING SYSTEMAbandonedFeb 22, 11Sep 01, 11[G06F]
7673262 System and method for product yield predictionExpiredMay 13, 08Mar 02, 10[G06F]
7638247 Method for electron beam proximity effect correctionExpiredJun 22, 06Dec 29, 09[G03C, G03F]
2009/0140,762 LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTINGAbandonedFeb 10, 09Jun 04, 09[G01R]
7508071 Adjusting die placement on a semiconductor wafer to increase yieldExpiredDec 22, 06Mar 24, 09[H01L]
7489151 Layout for DUT arrays used in semiconductor wafer testingExpiredOct 03, 05Feb 10, 09[G01R]
7487474 Designing an integrated circuit to improve yield using a variant design elementExpiredNov 17, 03Feb 03, 09[G06F]
2008/0312,875 Monitoring and control of integrated circuit device fabrication processesAbandonedJun 12, 07Dec 18, 08[G06F]
7334205 Optimization of die placement on wafersExpiredNov 22, 04Feb 19, 08[G06F]
7305638 Method and system for ROM coding to improve yieldExpiredMay 13, 05Dec 04, 07[G06F]
2007/0268,731 Layout compilerAbandonedMay 22, 06Nov 22, 07[G11C]
7220605 Selecting dice to test using a yield mapExpiredJul 28, 04May 22, 07[H01L]
7197726 Test structures for estimating dishing and erosion effects in copper damascene technologyExpiredSep 27, 02Mar 27, 07[G06F]
7169638 Adjusting die placement on a semiconductor wafer to increase yieldExpiredMar 16, 04Jan 30, 07[H01L]
2006/0278,956 Semiconductor wafer with non-rectangular shaped diceAbandonedMar 12, 04Dec 14, 06[H01L]
2006/0253,810 Integrated circuit design to optimize manufacturabilityAbandonedSep 16, 03Nov 09, 06[G06F]
7087507 Implantation of deuterium in MOS and DRAM devicesExpiredMay 17, 04Aug 08, 06[H01L]
7047505 Method for optimizing the characteristics of integrated circuits components from circuit specificationsExpiredOct 16, 01May 16, 06[G06F]

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