PROMOS TECHNOLOGIES INC.

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Technologies

Intl Class Technology # of Patents Rank
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 36871
 
 
 
G11C STATIC STORES 8366
 
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 2826
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 23284
 
 
 
H03K PULSE TECHNIQUE 2186
 
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 1173
 
 
 
G11B INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER 9118
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 861
 
 
 
C23C COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL 657
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 6120

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
6,855,610 Method of forming self-aligned contact structure with locally etched gate conductive layerDec 27, 02Feb 15, 05[H01L]184
6,355,524 Nonvolatile memory structures and fabrication methodsAug 15, 00Mar 12, 02[H01L]90
6,303,436 Method for fabricating a type of trench mask ROM cellSep 21, 99Oct 16, 01[H01L]80
6,265,269 Method for fabricating a concave bottom oxide in a trenchAug 06, 99Jul 24, 01[H01L]77
5,950,223 Dual-edge extended data out memoryJun 19, 97Sep 07, 99[G06F]58
6,040,216 Method (and device) for producing tunnel silicon oxynitride layerFeb 05, 98Mar 21, 00[H01L]52
6,069,507 Circuit and method for reducing delay line length in delay-locked loopsMay 22, 98May 30, 00[H03L]50
5,345,195 Low power V.sub.cc and temperature independent oscillatorOct 22, 92Sep 06, 94[H03K]50
5,934,974 In-situ monitoring of polishing pad wearNov 05, 97Aug 10, 99[B24B]49
6,632,742 Method for avoiding defects produced in the CMP processApr 18, 01Oct 14, 03[H01L]48

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2012/0008,444 DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAMJul 12, 10Jan 12, 12[G11C]
2012/0008,445 DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTEGRATED CIRCUIT DEVICES AND DEVICES INCORPORATING EMBEDDED DRAMJul 12, 10Jan 12, 12[G11C, H05K]
2011/0095,344 Method of Improving Minority Lifetime in Silicon Channel and Products ThereofNov 05, 10Apr 28, 11[H01L]
2010/0123,494 CONFIGURABLE ARCHITECTURE HYBRID ANALOG/DIGITAL DELAY LOCKED LOOP (DLL) AND TECHNIQUE WITH FAST OPEN LOOP DIGITAL LOCKING FOR INTEGRATED CIRCUIT DEVICESNov 20, 08May 20, 10[H03L]
2010/0060,315 HIGH CAPACITIVE LOAD AND NOISE TOLERANT SYSTEM AND METHOD FOR CONTROLLING THE DRIVE STRENGTH OF OUTPUT DRIVERS IN INTEGRATED CIRCUIT DEVICESSep 09, 08Mar 11, 10[G01R, H03K]
2010/0062,593 METHOD FOR PREPARING MULTI-LEVEL FLASH MEMORY DEVICESSep 10, 08Mar 11, 10[H01L]
2010/0050,939 METHOD FOR DETERMINING THE PERFORMANCE OF IMPLANTING APPARATUSAug 26, 08Mar 04, 10[B05C]
2010/0045,774 SOLID-STATE PANORAMIC IMAGE CAPTURE APPARATUSAug 21, 09Feb 25, 10[H04N, G02B]
2010/0047,994 FABRICATION OF INTEGRATED CIRCUITS WITH ISOLATION TRENCHESAug 21, 08Feb 25, 10[H01L]
2010/0038,745 INTEGRATED CIRCUIT STRUCTURE HAVING BOTTLE-SHAPED ISOLATIONAug 18, 08Feb 18, 10[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,339,882 Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAMJul 12, 10Dec 25, 12[G11C]
8,305,425 Solid-state panoramic image capture apparatusAug 21, 09Nov 06, 12[H04N, G02B]
8,283,733 Semiconductor devices with gate electrodes and with monocrystalline silicon regions that contain atoms of nitrogen and one or more of chlorine, bromine, sulfur, fluorine, or phosphorusNov 05, 10Oct 09, 12[H01L]
8,216,877 Phase-change memory and fabrication method thereofApr 05, 11Jul 10, 12[H01L]
8,125,020 Non-volatile memory devices with charge storage regionsOct 15, 07Feb 28, 12[H01L]
8,103,978 Method for establishing scattering bar ruleAug 26, 08Jan 24, 12[G06F]
8,071,970 Phase change memory device and fabrication method thereofDec 04, 08Dec 06, 11[H01L]
7,989,795 Phase change memory device and method for fabricating the sameSep 18, 07Aug 02, 11[H01L]
7,932,565 Integrated circuit structure having bottle-shaped isolationAug 18, 08Apr 26, 11[H01L]
7,919,384 Method of making planar-type bottom electrode for semiconductor deviceMar 18, 08Apr 05, 11[H01L]

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Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
Ding Yi
Sunnyvale, CA
34
Li Li-Chun
San Jose, CA
34
Faue Jon Allan
Colorado Springs, CO
33
Wu Hsiao-Che
Taoyuan Hsien, TW
26
Hsiao Chia-Shun
Cupertino, CA
24
Chen Min-Liang
Not Provided
22
Sung Kuo-Tung
Hsinchu, TW
22
Dong Zhong
Sunnyvale, CA
21
Ding Yi
Not Provided
19
Faue Jon Allan
Not Provided
17