QUALCOMM TECHNOLOGIES, INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 26413
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1654
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 14265
 
 
 
H01Q AERIALS 1298
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 6153
 
 
 
H04B TRANSMISSION 6196
 
 
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 3192
 
 
 
G11C STATIC STORES 3155
 
 
 
G09G ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION 2150
 
 
 
H01G CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE 263

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0091,513 HIGH-RESOLUTION ELECTRIC FIELD SENSOR IN COVER GLASSDec 14, 16Mar 30, 17[G06F, G06K]
2016/0232,704 APPARATUS AND METHOD FOR DISPLAYING AN IMAGE OF AN OBJECT ON A VISUAL DISPLAY UNITMay 09, 12Aug 11, 16[G06T, G09G]
2016/0126,934 SWITCHABLE CAPACITOR ARRAY AND METHOD FOR DRIVING A SWITCHABLE CAPACITOR ARRAYJun 19, 13May 05, 16[H03J, H03H]
2015/0346,251 DETECTOR CIRCUITJan 10, 13Dec 03, 15[G01R]
2015/0309,098 DETECTOR CIRCUITApr 25, 14Oct 29, 15[G01R]
2015/0293,159 MULTI-BAND IMPEDANCE DETECTORNov 22, 12Oct 15, 15[G01R, H03H]
2015/0256,486 ZERO-LATENCY NETWORK ON CHIP (NOC)May 25, 15Sep 10, 15[H04L]
2014/0052,956 STLB PREFETCHING FOR A MULTI-DIMENSION ENGINEAug 17, 13Feb 20, 14[G06F]
2013/0111,149 INTEGRATED CIRCUITS WITH CACHE-COHERENCYOct 24, 12May 02, 13[G06F]

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9760498 Hybrid cache comprising coherent and non-coherent linesSep 26, 14Sep 12, 17[G06F]
9728259 Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense marginMar 15, 16Aug 08, 17[G11C]
9639469 Coherency controller with reduced data bufferJul 13, 13May 02, 17[G06F]
9608935 Tunneling within a network-on-chip topologySep 08, 14Mar 28, 17[H04L, G06F]
9563560 Adaptive tuning of snoopsJul 10, 13Feb 07, 17[G06F]
9564856 Amplifier circuit with improved accuracyJan 09, 13Feb 07, 17[H03G, H03F]
9503222 Differential formatting between normal and retry data transmissionDec 07, 12Nov 22, 16[H04N, H04L, G06F, H03M]
9471538 Network on a chip socket protocolSep 25, 12Oct 18, 16[G06F]
9465749 DMA engine with STLB prefetch capabilities and tethered prefetchingAug 17, 13Oct 11, 16[G06F]
9426385 Image processing based on scene recognitionFeb 06, 15Aug 23, 16[H04N, G06K]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2016/0127,460 MULTI-HOP WIRELESS PEER-TO-PEER DISCOVERY PROTOCOLABANNov 03, 14May 05, 16[H04L, H04W]
2015/0019,193 VERIFICATION USING GENERIC PROTOCOL ADAPTERSABANJul 14, 13Jan 15, 15[G06F]
2015/0019,776 SELECTIVE CHANGE OF PENDING TRANSACTION URGENCYABANJul 14, 13Jan 15, 15[G06F]
2014/0095,807 ADAPTIVE TUNING OF SNOOPSABANJul 10, 13Apr 03, 14[G06F]
2013/0179,613 NETWORK ON CHIP (NOC) WITH QOS FEATURESABANNov 19, 12Jul 11, 13[G06F]
2013/0174,113 FLOORPLAN ESTIMATIONABANDec 20, 12Jul 04, 13[G06F]
2013/0002,315 ASYNCHRONOUS CLOCK ADAPTERABANJun 29, 12Jan 03, 13[H03L]
2013/0005,288 Circuit for Impedance MatchingABANSep 11, 12Jan 03, 13[H03H, H04B]
2012/0331,034 Latency ProbeABANJun 20, 12Dec 27, 12[G06F]
2012/0290,810 Memory Access Latency MeteringABANApr 18, 12Nov 15, 12[G06F]
2010/0180,163 METHOD AND DEVICE FOR SWITCHING BETWEEN AGENTSABANAug 11, 09Jul 15, 10[G06F]
2010/0122,004 MESSAGE SWITCHING SYSTEMABANNov 11, 09May 13, 10[G06F]
2008/0157,753 SYSTEM AND METHOD FOR DETERMINING THE PERFORMANCE OF AN ON-CHIP INTERCONNECTION NETWORKABANMay 17, 07Jul 03, 08[G01R]
2008/0028,090 System for managing messages transmitted in an on-chip interconnect networkABANSep 08, 06Jan 31, 08[G06F]
2007/0271,538 Process for designing a circuit for synchronizing data asychronously exchanged between two synchronous blocks, and synchronization circuit fabricated by sameABANJul 07, 06Nov 22, 07[G06F]
2007/0110,052 System and method for the static routing of data packet streams in an interconnect networkABANApr 19, 06May 17, 07[H04L]
2007/0081,414 System and method of on-circuit asynchronous communication, between synchronous subcircuitsABANApr 06, 06Apr 12, 07[G11C]
2007/0002,634 System and method of transmitting data in an electronic circuitABANJul 11, 05Jan 04, 07[G11C]
7148728 Digital delay device, digital oscillator clock signal generator and memory interfaceExpiredOct 01, 04Dec 12, 06[H03L]
2005/0157,717 Method and system for transmitting messages in an interconnection networkABANJan 19, 05Jul 21, 05[H04L]

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