RAMBUS INC.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 424128
 
 
 
G11C STATIC STORES 27032
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 14696
 
 
 
H03K PULSE TECHNIQUE 13237
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 74238
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7279
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 5928
 
 
 
H04B TRANSMISSION 58123
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 4328
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2879

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0023,118 RECONFIGURABLE MEMORY SYSTEM DATA STROBESOct 08, 14Jan 22, 15[G11C, G06F]
2015/0019,786 METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULESMay 22, 14Jan 15, 15[G06F]
2014/0376,304 RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODSSep 11, 14Dec 25, 14[G11C]
2014/0376,324 TESTING THROUGH-SILICON-VIASAug 31, 12Dec 25, 14[G01R, G11C]
2014/0376,364 TEMPORAL REDUNDANCYJul 20, 12Dec 25, 14[H04L]
2014/0380,082 INTEGRATED CIRCUIT COMPRISING FRACTIONAL CLOCK MULTIPLICATION CIRCUITRYSep 10, 14Dec 25, 14[H03B, G06F, H03L]
2014/0372,707 Wear Leveling in a Memory SystemDec 29, 12Dec 18, 14[G06F]
2014/0347,092 MODULATED ON-DIE TERMINATIONDec 22, 12Nov 27, 14[H03K]
2014/0347,108 METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALINGAug 11, 14Nov 27, 14[H03L]
2014/0347,950 Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory LocationsMar 03, 14Nov 27, 14[G11C]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,937,994 Partial response decision feedback equalizer with selection circuitry having hold stateJun 11, 13Jan 20, 15[H03H, H03K]
8,938,578 Memory device with multi-mode deserializerJul 08, 13Jan 20, 15[G11C, G06F]
8,933,729 Stacked receiversMar 15, 13Jan 13, 15[H03F, H03B, H03K]
8,934,525 High-speed signaling systems and methods with adaptable, continuous-time equalizationJan 07, 08Jan 13, 15[H03H, H04L, H03K]
8,935,489 Adaptively time-multiplexing memory references from multiple processor coresNov 10, 10Jan 13, 15[G06F]
8,929,159 Driver circuitApr 05, 12Jan 06, 15[G11C, H03L]
8,929,424 Periodic calibration for communication channels by drift trackingJan 01, 14Jan 06, 15[H04L, H04Q, H04B]
8,929,496 Receiver with enhanced clock and data recoveryJan 30, 09Jan 06, 15[H04L]
8,930,740 Regulation of memory IO timing using programmatic control over memory device IO timingNov 16, 10Jan 06, 15[G06F]
8,930,779 Bit-replacement technique for DRAM error correctionNov 10, 10Jan 06, 15[G11C, G06F]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0322,510 SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTSMay 13, 13Dec 05, 13[H04B]
2013/0168,674 Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated CircuitsDec 19, 12Jul 04, 13[H01L]
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTDec 22, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGESep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORApr 08, 12Nov 08, 12[H04N]
2012/0281,489 Low Power Memory DeviceMay 07, 12Nov 08, 12[G11C]
2012/0218,001 Techniques for Phase DetectionOct 31, 10Aug 30, 12[H03D]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkOct 11, 10Aug 23, 12[G06F]
2012/0191,943 DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATIONAug 29, 10Jul 26, 12[G06F]
2012/0182,304 Scalable Unified Memory ArchitectureMar 26, 12Jul 19, 12[G06F]
2012/0184,242 Methods and Systems for Enhancing Wireless CoverageAug 31, 10Jul 19, 12[H04W]
2012/0139,638 Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and TemperatureDec 02, 11Jun 07, 12[H03F]
2012/0013,361 Synthetic Pulse Generator for Reducing Supply NoiseJan 14, 10Jan 19, 12[H03K]
2012/0011,331 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOLMar 10, 10Jan 12, 12[G06F]
2011/0307,672 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATIONFeb 25, 10Dec 15, 11[G06F]
2011/0249,718 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMSDec 29, 09Oct 13, 11[H04L, H04B]
2011/0235,763 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATIONJul 09, 09Sep 29, 11[H04L]
2011/0238,870 Memory System With Command FilteringNov 17, 09Sep 29, 11[G06F]

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