RAMBUS INC.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 411128
 
 
 
G11C STATIC STORES 24833
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 14093
 
 
 
H03K PULSE TECHNIQUE 12535
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 75229
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7076
 
 
 
H04B TRANSMISSION 56127
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 5429
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 4125
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2778

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0301,151 DISTRIBUTED SUB-PAGE SELECTIONAug 27, 12Oct 09, 14[G11C]
2014/0285,232 Methods and Systems for Reducing Supply and Termination NoiseFeb 27, 14Sep 25, 14[H03K]
2014/0286,383 Selectable-tap EqualizerJan 01, 14Sep 25, 14[H04L, H04B]
2014/0286,389 Multiphase Receiver with Equalization CircuitryJan 17, 14Sep 25, 14[H04L]
2014/0286,450 MULTI-ANTENNA TRANSMITTER FOR MULTI-TONE SIGNALINGOct 29, 13Sep 25, 14[H04B]
2014/0289,574 DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTIONOct 19, 12Sep 25, 14[G11C]
2014/0267,884 Increasing Dynamic Range Using MultisamplingMar 15, 13Sep 18, 14[H04N]
2014/0269,006 FAST READ SPEED MEMORY DEVICEMar 13, 14Sep 18, 14[G11C]
2014/0281,205 MEMORY CIRCUIT AND METHOD FOR ITS OPERATIONApr 18, 12Sep 18, 14[G11C]
2014/0253,195 OPEN-LOOP CORRECTION OF DUTY-CYCLE ERROR AND QUADRATURE PHASE ERRORJan 27, 14Sep 11, 14[H03K]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,861,259 Resistance change memory cell circuits and methodsOct 26, 11Oct 14, 14[G11C]
8,861,667 Clock data recovery circuit with equalizer clock calibrationJul 12, 02Oct 14, 14[H04L]
8,854,091 Integrated circuit comprising fractional clock multiplication circuitryNov 27, 12Oct 07, 14[H03B, H03K]
8,855,217 Interface with variable data rateOct 01, 12Oct 07, 14[H04L, H04B]
8,856,480 Mechanism for enabling full data bus utilization without increasing data granularityDec 19, 12Oct 07, 14[G11C, G06F]
8,842,492 Memory components and controllers that utilize multiphase synchronous timing referencesNov 19, 11Sep 23, 14[H04L, G11C, G06F]
8,836,394 Method and apparatus for source-synchronous signalingJun 14, 12Sep 16, 14[H04L, G11C, H03L]
8,837,236 Hybrid nonvolatile shadowed DRAM with an overlapping region between a volatile storage die and a nonvolatile storage dieApr 22, 13Sep 16, 14[G11C, G06F]
8,838,900 Atomic-operation coalescing technique in multi-chip systemsJun 10, 13Sep 16, 14[G06F]
8,824,222 Fast-wake memoryAug 04, 11Sep 02, 14[G11C]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTDec 22, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGESep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORApr 08, 12Nov 08, 12[H04N]
2012/0281,489 Low Power Memory DeviceMay 07, 12Nov 08, 12[G11C]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkOct 11, 10Aug 23, 12[G06F]
2012/0191,943 DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATIONAug 29, 10Jul 26, 12[G06F]
2012/0182,304 Scalable Unified Memory ArchitectureMar 26, 12Jul 19, 12[G06F]
2012/0184,242 Methods and Systems for Enhancing Wireless CoverageAug 31, 10Jul 19, 12[H04W]
2012/0139,638 Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and TemperatureDec 02, 11Jun 07, 12[H03F]
2012/0013,361 Synthetic Pulse Generator for Reducing Supply NoiseJan 14, 10Jan 19, 12[H03K]
2012/0011,331 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOLMar 10, 10Jan 12, 12[G06F]
2011/0307,672 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATIONFeb 25, 10Dec 15, 11[G06F]
2011/0249,718 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMSDec 29, 09Oct 13, 11[H04L, H04B]
2011/0235,763 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATIONJul 09, 09Sep 29, 11[H04L]
2011/0238,870 Memory System With Command FilteringNov 17, 09Sep 29, 11[G06F]
2011/0202,709 OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORYMar 04, 09Aug 18, 11[G06F]
2011/0141,829 Circuits for Reducing Power Consumption of Memory ComponentsDec 14, 10Jun 16, 11[G11C, H03K]
2011/0119,425 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEMJun 30, 08May 19, 11[G06F]

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