RAMBUS INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 517124
 
 
 
G11C STATIC STORES 39126
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 20497
 
 
 
H03K PULSE TECHNIQUE 16133
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 90242
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7683
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 6525
 
 
 
H04B TRANSMISSION 65128
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 4430
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 3773

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0147,281 MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODESNov 24, 15May 26, 16[G06F]
2016/0147,481 BUFFER CIRCUIT WITH DATA BIT INVERSIONApr 25, 14May 26, 16[G06F]
2016/0148,671 MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATIONNov 24, 15May 26, 16[G11C]
2016/0149,730 EQUALIZED MULTI-SIGNALING MODE DRIVERNov 25, 15May 26, 16[H04L]
2016/0142,053 Calibration Methods and Circuits to Calibrate Drive Current and Termination ImpedanceOct 15, 15May 19, 16[H04L, H03K]
2016/0142,200 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer TimingSep 29, 15May 19, 16[H04L]
2016/0132,241 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACEJan 19, 16May 12, 16[G06F]
2016/0132,439 EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEMOct 02, 15May 12, 16[G06F]
2016/0134,440 Partial Response Receiver and Related MethodNov 10, 15May 12, 16[H04L, H03K]
2016/0134,442 Decision Feedback EqualizerNov 11, 15May 12, 16[H04L, H03M]
2016/0124,895 Interface with Variable Data RateNov 03, 15May 05, 16[G06F]
2016/0125,929 METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLERSep 09, 15May 05, 16[G11C]
2016/0125,930 METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEMNov 03, 15May 05, 16[G11C]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,349,422 Supporting calibration for sub-rate operation in clocked memory systemsApr 15, 15May 24, 16[G11C, G06F]
9,350,421 Configurable, power supply voltage referenced single-ended signaling with ESD protectionNov 05, 13May 24, 16[H04L, G06F, H04B, H03K]
9,342,095 Timing calibration for multimode I/O systemsFeb 24, 12May 17, 16[G11C, G06F]
9,344,064 Integrated circuit comprising frequency change detection circuitryJul 24, 15May 17, 16[G01R, G11C, H03K, H03L]
9,344,074 Low-latency, frequency-agile clock multiplierDec 10, 14May 17, 16[H03K, H03L]
9,344,635 Conditional-reset, temporally oversampled image sensorNov 08, 12May 17, 16[H04N]
9,336,834 Offsetting clock package pins in a clamshell topology to improve signal integrityFeb 07, 12May 10, 16[G11C, H01L, H05K]
9,337,835 Controlling a flash device having time-multiplexed, on-die-terminated signaling interfaceSep 17, 15May 10, 16[G11C, G06F, H03K]
9,337,872 Configurable, error-tolerant memory controlMar 10, 12May 10, 16[G06F, H03M]
9,337,992 Clock and data recovery using receiver clock spread spectrum modulation and offset compensationDec 17, 14May 10, 16[H04L, H03L]
9,338,037 Integrated circuit with configurable on-die terminationJan 16, 15May 10, 16[H04L, H03K]
9,330,034 Levelization of memory interface for communicating with multiple memory devicesMar 30, 11May 03, 16[G06F]
9,330,735 Memory with deferred fractional row activationJun 08, 12May 03, 16[G11C]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2014/0314,406 Systems and Methods for Temperature Insensitive Photonic TransmissionABANNov 30, 12Oct 23, 14[H04J, H04B]
2014/0286,383 Selectable-tap EqualizerABANJan 01, 14Sep 25, 14[H04L, H04B]
2014/0219,008 Semiconductor Memory Device with Hierarchical BitlinesABANApr 04, 14Aug 07, 14[G11C]
2014/0071,329 RECONFIGURABLE OPTICAL DEVICE USING A TOTAL INTERNAL REFLECTION (TIR) OPTICAL SWITCHABANSep 06, 13Mar 13, 14[H04N, G02B]
2013/0346,822 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATIONABANJun 10, 13Dec 26, 13[H03M]
2013/0322,510 SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTSABANMay 13, 13Dec 05, 13[H04B]
2013/0290,494 SESSION MANAGEMENT FOR COMMUNICATION IN A HETEROGENEOUS NETWORKABANOct 20, 11Oct 31, 13[H04L]
2013/0250,657 System and Method for Writing Data to an RRAM CellABANMar 07, 13Sep 26, 13[G11C]
2013/0168,674 Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated CircuitsABANDec 19, 12Jul 04, 13[H01L]
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTABANDec 22, 12Jun 13, 13[G11C]
2013/0148,447 Reducing Power Consumption in a Memory SystemABANDec 06, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGEABANSep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionABANSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSABANJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORABANApr 08, 12Nov 08, 12[H04N]
2012/0281,489 Low Power Memory DeviceABANMay 07, 12Nov 08, 12[G11C]
2012/0218,001 Techniques for Phase DetectionABANOct 31, 10Aug 30, 12[H03D]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkABANOct 11, 10Aug 23, 12[G06F]
2012/0201,089 INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRST CODE, A STROBE SIGNAL AFTER A DELAY AND DATA TO A DYNAMIC RANDOM ACCESS MEMORY (DRAM)ABANApr 19, 12Aug 09, 12[G11C]
2012/0191,943 DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATIONABANAug 29, 10Jul 26, 12[G06F]

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