RAMBUS INC.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 413128
 
 
 
G11C STATIC STORES 25631
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 14190
 
 
 
H03K PULSE TECHNIQUE 12735
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 77223
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7170
 
 
 
H04B TRANSMISSION 58125
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 5528
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 4126
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2779

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0333,341 TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICESApr 10, 14Nov 13, 14[G01R]
2014/0333,356 Signal Distribution Networks and Related MethodsNov 25, 13Nov 13, 14[H03L]
2014/0333,361 EVENT-DRIVEN CLOCK DUTY CYCLE CONTROLNov 16, 12Nov 13, 14[H03K]
2014/0333,386 INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATORJul 28, 14Nov 13, 14[H03L]
2014/0334,236 LOW-POWER SOURCE-SYNCHRONOUS SIGNALINGJul 28, 14Nov 13, 14[G11C]
2014/0334,238 Low Power Memory DeviceFeb 05, 14Nov 13, 14[G11C]
2014/0337,645 FAST-WAKE MEMORYJul 29, 14Nov 13, 14[G11C, G06F]
2014/0329,359 PROCESS FOR MAKING A SEMICONDUCTOR SYSTEMMay 07, 14Nov 06, 14[H01L]
2014/0331,112 Margin Test Methods and CircuitsJul 17, 14Nov 06, 14[G06F]
2014/0313,387 IMAGE SENSOR SAMPLED AT NON-UNIFORM INTERVALSNov 08, 12Oct 23, 14[H04N]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,885,423 DRAM sense amplifier that supports low memory-cell capacitanceNov 19, 10Nov 11, 14[G11C, H01L]
8,878,592 Simultaneous switching noise cancellation by adjusting reference voltage and sampling clock phaseApr 26, 13Nov 04, 14[G11C, H03K]
8,879,724 Differential power analysis—resistant cryptographic processingDec 14, 09Nov 04, 14[H04L, G06Q, G06F, G07F, G06K]
8,880,818 Reconfigurable memory controllerJan 29, 14Nov 04, 14[G06F]
8,873,329 Patterned memory page activationJan 14, 13Oct 28, 14[G11C]
8,865,287 Rapid curing aldehyde resin-polyisocyanate composition and method for producing hybrid polymerAug 12, 09Oct 21, 14[C08G, C08F, C09D, B05D, B32B]
8,867,595 Reference voltage generation and calibration for single-ended signalingJun 10, 13Oct 21, 14[H04B, H03K]
8,868,873 Reconfigurable memory system data strobesAug 25, 08Oct 21, 14[G06F]
8,861,259 Resistance change memory cell circuits and methodsOct 26, 11Oct 14, 14[G11C]
8,861,667 Clock data recovery circuit with equalizer clock calibrationJul 12, 02Oct 14, 14[H04L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTDec 22, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGESep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORApr 08, 12Nov 08, 12[H04N]
2012/0281,489 Low Power Memory DeviceMay 07, 12Nov 08, 12[G11C]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkOct 11, 10Aug 23, 12[G06F]
2012/0191,943 DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATIONAug 29, 10Jul 26, 12[G06F]
2012/0182,304 Scalable Unified Memory ArchitectureMar 26, 12Jul 19, 12[G06F]
2012/0184,242 Methods and Systems for Enhancing Wireless CoverageAug 31, 10Jul 19, 12[H04W]
2012/0139,638 Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and TemperatureDec 02, 11Jun 07, 12[H03F]
2012/0013,361 Synthetic Pulse Generator for Reducing Supply NoiseJan 14, 10Jan 19, 12[H03K]
2012/0011,331 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOLMar 10, 10Jan 12, 12[G06F]
2011/0307,672 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATIONFeb 25, 10Dec 15, 11[G06F]
2011/0249,718 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMSDec 29, 09Oct 13, 11[H04L, H04B]
2011/0235,763 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATIONJul 09, 09Sep 29, 11[H04L]
2011/0238,870 Memory System With Command FilteringNov 17, 09Sep 29, 11[G06F]
2011/0202,709 OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORYMar 04, 09Aug 18, 11[G06F]
2011/0141,829 Circuits for Reducing Power Consumption of Memory ComponentsDec 14, 10Jun 16, 11[G11C, H03K]
2011/0119,425 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEMJun 30, 08May 19, 11[G06F]

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