RAMBUS INC.

Patent Owner

Compare Create Portfolio
18Status Updates

Stats

Details

Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 404127
 
 
 
G11C STATIC STORES 24034
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 13493
 
 
 
H03K PULSE TECHNIQUE 12338
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 75231
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7075
 
 
 
H04B TRANSMISSION 56131
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 5530
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 4026
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2777

Top Patents (by citation)

Upgrade to the Premium Level to View Top Patents for this Owner. Learn More

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0226,420 STROBE-OFFSET CONTROL CIRCUITMar 31, 14Aug 14, 14[G11C]
2014/0226,707 OFFSET AND DECISION FEEDBACK EQUALIZATION CALIBRATIONAug 10, 12Aug 14, 14[H04L, H04B]
2014/0229,667 Memory System with Calibrated Data CommunicationJan 13, 14Aug 14, 14[G11C]
2014/0218,120 ELECTRONIC CIRCUITS USING COUPLED MULTI-INDUCTORSAug 29, 12Aug 07, 14[H01F, H03B, H03K]
2014/0219,008 Semiconductor Memory Device with Hierarchical BitlinesApr 04, 14Aug 07, 14[G11C]
2014/0223,068 Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory DeviceAug 30, 13Aug 07, 14[G06F]
2014/0223,269 MEMORY CONTROLLER WITH WRITE DATA ERROR DETECTION AND REMEDIATIONFeb 07, 14Aug 07, 14[G06F]
2014/0210,545 ON-CHIP REGULATOR WITH VARIABLE LOAD COMPENSATIONAug 31, 12Jul 31, 14[G05F]
2014/0210,683 CALIBRATING A RETRO-DIRECTIVE ARRAY FOR AN ASYMMETRIC WIRELESS LINKJul 20, 12Jul 31, 14[H01Q]
2014/0208,188 Variable Code Rate TransmissionAug 09, 12Jul 24, 14[G06F]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,811,095 Methods and circuits for dynamically scaling DRAM power and performanceDec 01, 10Aug 19, 14[G11C]
8,811,553 Edge based partial response equalizationJul 01, 13Aug 19, 14[H03H, H04L, H04B]
8,812,918 Method and apparatus for evaluating and optimizing a signaling systemNov 07, 11Aug 19, 14[G01R, H04L, G11C, G06F, H04B]
8,812,919 Method and apparatus for evaluating and optimizing a signaling systemJun 12, 13Aug 19, 14[G01R, H04L, G11C, G06F, H04B]
8,804,394 Stacked memory with redundancyDec 27, 12Aug 12, 14[G11C]
8,804,397 Integrated circuit having a clock deskew circuit that includes an injection-locked oscillatorJan 19, 12Aug 12, 14[G11C]
8,806,659 Secure remote content activation and unlockingMay 22, 09Aug 12, 14[G06F]
8,795,082 Directional beam steering system and method to detect location and motionJan 13, 11Aug 05, 14[A63F]
8,793,525 Low-power source-synchronous signalingJul 03, 08Jul 29, 14[G06F]
8,782,578 Generating interface adjustment signals in a device-to-device interconnection systemJan 22, 13Jul 15, 14[G06F]

View all patents..

Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTDec 22, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGESep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORApr 08, 12Nov 08, 12[H04N]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkOct 11, 10Aug 23, 12[G06F]
2012/0182,304 Scalable Unified Memory ArchitectureMar 26, 12Jul 19, 12[G06F]
2012/0139,638 Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and TemperatureDec 02, 11Jun 07, 12[H03F]
2012/0013,361 Synthetic Pulse Generator for Reducing Supply NoiseJan 14, 10Jan 19, 12[H03K]
2012/0011,331 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOLMar 10, 10Jan 12, 12[G06F]
2011/0307,672 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATIONFeb 25, 10Dec 15, 11[G06F]
2011/0249,718 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMSDec 29, 09Oct 13, 11[H04L, H04B]
2011/0235,763 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATIONJul 09, 09Sep 29, 11[H04L]
2011/0238,870 Memory System With Command FilteringNov 17, 09Sep 29, 11[G06F]
2011/0202,709 OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORYMar 04, 09Aug 18, 11[G06F]
2011/0141,829 Circuits for Reducing Power Consumption of Memory ComponentsDec 14, 10Jun 16, 11[G11C, H03K]
2011/0119,425 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEMJun 30, 08May 19, 11[G06F]
2011/0066,792 Segmentation Of Flash Memory For Partial Volatile StorageFeb 04, 09Mar 17, 11[G06F]
2011/0060,868 MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCESFeb 10, 09Mar 10, 11[G06F]
2011/0030,161 PAINT ROLLER AND PAINT ROLLER SLEEVE SUPPORTOct 30, 07Feb 10, 11[B05C]

View all patents..

Top Inventors for This Owner

Upgrade to the Premium Level to View Top Inventors for this Owner. Learn More

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to -1 comparisons!

We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.