RAMBUS INC.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 416130
 
 
 
G11C STATIC STORES 25934
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 14192
 
 
 
H03K PULSE TECHNIQUE 12934
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 75245
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7173
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 5931
 
 
 
H04B TRANSMISSION 58122
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 4130
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2779

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0347,092 MODULATED ON-DIE TERMINATIONDec 22, 12Nov 27, 14[H03K]
2014/0347,108 METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALINGAug 11, 14Nov 27, 14[H03L]
2014/0347,950 Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory LocationsMar 03, 14Nov 27, 14[G11C]
2014/0351,629 MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKINGMay 22, 14Nov 27, 14[G06F]
2014/0351,673 DRAM METHOD, COMPONENTS, AND SYSTEM CONFIGURATIONS FOR ERROR MANAGEMENTMay 22, 14Nov 27, 14[G06F]
2014/0340,120 Techniques for Phase DetectionAug 05, 14Nov 20, 14[H03D]
2014/0341,266 METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATIONMar 26, 14Nov 20, 14[H04L]
2014/0344,546 Memory Controller For Micro-Threaded Memory OperationsAug 01, 14Nov 20, 14[G11C, G06F]
2014/0333,341 TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICESApr 10, 14Nov 13, 14[G01R]
2014/0333,356 Signal Distribution Networks and Related MethodsNov 25, 13Nov 13, 14[H03L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,908,407 Content addressable memory (“CAM”)Jul 13, 12Dec 09, 14[G11C]
8,908,454 Memory architecture with redundant resourcesAug 20, 12Dec 09, 14[G11C]
8,908,466 Multi-column addressing mode memory system including an integrated circuit memory deviceApr 11, 13Dec 09, 14[G11C]
8,901,975 Digital PLL with dynamic loop gain controlAug 06, 13Dec 02, 14[G11C, H03L]
8,903,031 Low jitter clock recovery circuitMay 17, 13Dec 02, 14[H04L, H03D, H03L]
8,896,355 Clock multiplier with dynamically tuned lock rangeFeb 04, 14Nov 25, 14[H03B, H03L]
8,890,580 Methods and circuits for reducing clock jitterOct 03, 11Nov 18, 14[H03B, H03K, H03L]
8,885,423 DRAM sense amplifier that supports low memory-cell capacitanceNov 19, 10Nov 11, 14[G11C, H01L]
8,878,592 Simultaneous switching noise cancellation by adjusting reference voltage and sampling clock phaseApr 26, 13Nov 04, 14[G11C, H03K]
8,879,724 Differential power analysis—resistant cryptographic processingDec 14, 09Nov 04, 14[H04L, G06Q, G06F, G07F, G06K]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTDec 22, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGESep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORApr 08, 12Nov 08, 12[H04N]
2012/0281,489 Low Power Memory DeviceMay 07, 12Nov 08, 12[G11C]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkOct 11, 10Aug 23, 12[G06F]
2012/0191,943 DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATIONAug 29, 10Jul 26, 12[G06F]
2012/0182,304 Scalable Unified Memory ArchitectureMar 26, 12Jul 19, 12[G06F]
2012/0184,242 Methods and Systems for Enhancing Wireless CoverageAug 31, 10Jul 19, 12[H04W]
2012/0139,638 Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and TemperatureDec 02, 11Jun 07, 12[H03F]
2012/0013,361 Synthetic Pulse Generator for Reducing Supply NoiseJan 14, 10Jan 19, 12[H03K]
2012/0011,331 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOLMar 10, 10Jan 12, 12[G06F]
2011/0307,672 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATIONFeb 25, 10Dec 15, 11[G06F]
2011/0249,718 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMSDec 29, 09Oct 13, 11[H04L, H04B]
2011/0235,763 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATIONJul 09, 09Sep 29, 11[H04L]
2011/0238,870 Memory System With Command FilteringNov 17, 09Sep 29, 11[G06F]
2011/0202,709 OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORYMar 04, 09Aug 18, 11[G06F]
2011/0141,829 Circuits for Reducing Power Consumption of Memory ComponentsDec 14, 10Jun 16, 11[G11C, H03K]
2011/0119,425 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEMJun 30, 08May 19, 11[G06F]

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