RAMBUS INC.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 401128
 
  
 
G11C STATIC STORES 22737
 
  
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 12993
 
  
 
H03K PULSE TECHNIQUE 12138
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 69234
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 6574
 
  
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 5429
 
  
 
H04B TRANSMISSION 52125
 
  
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 3629
 
  
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2777

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0192,940 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONSMar 07, 14Jul 10, 14[H04L]
2014/0185,362 SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLSAug 10, 12Jul 03, 14[G11C]
2014/0185,725 DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELSJul 23, 13Jul 03, 14[H04L]
2014/0189,466 Memory Error DetectionMar 07, 14Jul 03, 14[G06F]
2014/0175,264 Pixel Structure and Reset SchemeDec 19, 13Jun 26, 14[H01L]
2014/0181,331 Reconfigurable Memory ControllerJan 29, 14Jun 26, 14[G06F]
2014/0181,393 Memory Systems and Methods for Dynamically Phase Adjusting a Write Strobe and Data to Account for Receive-Clock DriftOct 07, 13Jun 26, 14[G11C]
2014/0169,438 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer TimingAug 29, 13Jun 19, 14[H04L]
2014/0173,238 Methods and Circuits for Securing Proprietary Memory TransactionsDec 06, 13Jun 19, 14[G06F]
2014/0173,240 MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUTJan 13, 14Jun 19, 14[G11C, G06F]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,782,578 Generating interface adjustment signals in a device-to-device interconnection systemJan 22, 13Jul 15, 14[G06F]
8,773,925 Multilevel DRAMDec 01, 10Jul 08, 14[G11C]
8,774,337 Phase control block for managing multiple clock domains in systems with frequency offsetsDec 10, 12Jul 08, 14[H04L]
8,775,705 Chip having register to store value that represents adjustment to reference voltageMar 29, 13Jul 08, 14[G06F]
8,766,434 Semiconductor module with micro-buffersJan 16, 13Jul 01, 14[H01L]
8,766,647 Method and apparatus for power sequence timing to mitigate supply resonance in power distribution networkMay 05, 09Jul 01, 14[G01R, G11C]
8,769,234 Memory modules and devices supporting configurable data widthsFeb 27, 13Jul 01, 14[G06F]
8,760,944 Memory component that samples command/address signals in response to both edges of a clock signalJun 21, 13Jun 24, 14[G11C]
8,762,657 Method and system for synchronizing address and control signals in threaded memory modulesJul 01, 10Jun 24, 14[G06F]
8,762,691 Memory access consolidation for SIMD processing elements using transaction identifiersJun 29, 07Jun 24, 14[G06F]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTDec 22, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGESep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORApr 08, 12Nov 08, 12[H04N]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkOct 11, 10Aug 23, 12[G06F]
2012/0182,304 Scalable Unified Memory ArchitectureMar 26, 12Jul 19, 12[G06F]
2012/0139,638 Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and TemperatureDec 02, 11Jun 07, 12[H03F]
2012/0013,361 Synthetic Pulse Generator for Reducing Supply NoiseJan 14, 10Jan 19, 12[H03K]
2012/0011,331 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOLMar 10, 10Jan 12, 12[G06F]
2011/0307,672 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATIONFeb 25, 10Dec 15, 11[G06F]
2011/0249,718 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMSDec 29, 09Oct 13, 11[H04L, H04B]
2011/0235,763 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATIONJul 09, 09Sep 29, 11[H04L]
2011/0238,870 Memory System With Command FilteringNov 17, 09Sep 29, 11[G06F]
2011/0202,709 OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORYMar 04, 09Aug 18, 11[G06F]
2011/0141,829 Circuits for Reducing Power Consumption of Memory ComponentsDec 14, 10Jun 16, 11[G11C, H03K]
2011/0119,425 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEMJun 30, 08May 19, 11[G06F]
2011/0066,792 Segmentation Of Flash Memory For Partial Volatile StorageFeb 04, 09Mar 17, 11[G06F]
2011/0060,868 MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCESFeb 10, 09Mar 10, 11[G06F]
2011/0030,161 PAINT ROLLER AND PAINT ROLLER SLEEVE SUPPORTOct 30, 07Feb 10, 11[B05C]

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