RAMBUS INC.

Patent Owner

Compare Create Portfolio
10Status Updates

Stats

Details

Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 431129
 
 
 
G11C STATIC STORES 27831
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 14795
 
 
 
H03K PULSE TECHNIQUE 13334
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 74237
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7276
 
 
 
H04B TRANSMISSION 57128
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 5630
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 4328
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2879

Top Patents (by citation)

Upgrade to the Premium Level to View Top Patents for this Owner. Learn More

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0049,798 RECEIVER WITH ENHANCED ISI MITIGATIONNov 30, 12Feb 19, 15[H04L, H04B]
2015/0042,378 BUFFERED MEMORY MODULE HAVING MULTI-VALUED ON-DIE TERMINATIONOct 26, 14Feb 12, 15[G11C, H03K]
2015/0043,290 MEMORY MODULEOct 26, 14Feb 12, 15[G11C]
2015/0036,732 EDGE BASED PARTIAL RESPONSE EQUALIZATIONAug 19, 14Feb 05, 15[H04L]
2015/0036,775 METHODS AND CIRCUITS FOR REDUCING CLOCK JITTEROct 20, 14Feb 05, 15[H04L]
2015/0039,822 MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITYSep 03, 14Feb 05, 15[G11C, G06F]
2015/0033,044 Methods and Circuits for Dynamically Scaling DRAM Power and PerformanceAug 05, 14Jan 29, 15[G11C, G06F]
2015/0023,118 RECONFIGURABLE MEMORY SYSTEM DATA STROBESOct 08, 14Jan 22, 15[G11C, G06F]
2015/0019,786 METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULESMay 22, 14Jan 15, 15[G06F]
2014/0376,304 RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODSSep 11, 14Dec 25, 14[G11C]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,964,879 Crosstalk reduction coding schemesJul 09, 13Feb 24, 15[H04L, H04B]
8,947,962 On-die termination of address and command signalsNov 22, 13Feb 03, 15[G11C]
8,948,212 Memory controller with circuitry to set memory device-specific reference voltagesJan 13, 14Feb 03, 15[H04L, G11C, G06F]
8,949,520 Maintenance operations in a DRAMJan 13, 10Feb 03, 15[G11C, G06Q, G06F]
8,941,407 Integrated circuit with configurable on-die terminationMay 30, 13Jan 27, 15[H04L, H03K]
8,941,420 Low-latency, frequency-agile clock multiplierMay 24, 12Jan 27, 15[H03B, H03K, H03L]
8,942,056 Protocol for memory power-mode controlFeb 15, 12Jan 27, 15[G11C, G06F]
8,942,297 Forwarding signal supply voltage in data transmission systemMar 30, 10Jan 27, 15[H04L, G11C, G06F, H04B]
8,942,309 Signal output improvement using data inversion and/or swappingApr 15, 13Jan 27, 15[H04L]
8,942,319 Partial response equalizer and related methodMar 25, 11Jan 27, 15[H04L, H03D]

View all patents..

Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0346,822 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATIONJun 10, 13Dec 26, 13[H03M]
2013/0322,510 SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTSMay 13, 13Dec 05, 13[H04B]
2013/0168,674 Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated CircuitsDec 19, 12Jul 04, 13[H01L]
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTDec 22, 12Jun 13, 13[G11C]
2013/0072,171 ENHANCING MOBILE DEVICE COVERAGESep 13, 12Mar 21, 13[H04W]
2013/0063,191 Methods and Circuits for Duty-Cycle CorrectionSep 12, 12Mar 14, 13[H03K, H03L]
2012/0306,568 REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTSJun 05, 12Dec 06, 12[H03K]
2012/0281,126 DIGITAL INTEGRATION SENSORApr 08, 12Nov 08, 12[H04N]
2012/0281,489 Low Power Memory DeviceMay 07, 12Nov 08, 12[G11C]
2012/0218,001 Techniques for Phase DetectionOct 31, 10Aug 30, 12[H03D]
2012/0215,952 Protocol for Transmission of Data Over a Communication LinkOct 11, 10Aug 23, 12[G06F]
2012/0191,943 DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATIONAug 29, 10Jul 26, 12[G06F]
2012/0182,304 Scalable Unified Memory ArchitectureMar 26, 12Jul 19, 12[G06F]
2012/0184,242 Methods and Systems for Enhancing Wireless CoverageAug 31, 10Jul 19, 12[H04W]
2012/0139,638 Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and TemperatureDec 02, 11Jun 07, 12[H03F]
2012/0013,361 Synthetic Pulse Generator for Reducing Supply NoiseJan 14, 10Jan 19, 12[H03K]
2012/0011,331 MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOLMar 10, 10Jan 12, 12[G06F]
2011/0307,672 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATIONFeb 25, 10Dec 15, 11[G06F]
2011/0249,718 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMSDec 29, 09Oct 13, 11[H04L, H04B]
2011/0235,763 SIGNALING SYSTEM WITH ASYMMETRICALLY-MANAGED TIMING CALIBRATIONJul 09, 09Sep 29, 11[H04L]

View all patents..

Top Inventors for This Owner

Upgrade to the Premium Level to View Top Inventors for this Owner. Learn More

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to -1 comparisons!

We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.