RAMBUS INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 601115
 
  
 
G11C STATIC STORES 48222
 
  
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 23995
 
  
 
H03K PULSE TECHNIQUE 17530
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 106243
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 8481
 
  
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 8122
 
  
 
H04B TRANSMISSION 76125
 
  
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 5222
 
  
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 4565

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0199,242 Technique for Determining Performance Characteristics Of Electronic Devices And SystemsDec 22, 16Jul 13, 17[G01R, G11C]
2017/0200,489 METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEMJan 13, 17Jul 13, 17[G11C]
2017/0192,912 Clock Generation for Timing Communications with Ranks of Memory DevicesFeb 03, 17Jul 06, 17[G11C, G06F]
2017/0194,036 Forwarding Signal Supply Voltage in Data Transmission SystemDec 27, 16Jul 06, 17[G11C, G06F]
2017/0195,596 OVERSAMPLED HIGH DYNAMIC-RANGE IMAGE SENSORMay 21, 15Jul 06, 17[H04N, G06T]
2017/0177,021 DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICEDec 27, 16Jun 22, 17[G06F]
2017/0177,487 DETERMINISTIC OPERATION OF STORAGE CLASS MEMORYDec 12, 16Jun 22, 17[G06F]
2017/0177,540 Interface with Variable Data RateDec 28, 16Jun 22, 17[G06F]
2017/0178,702 MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATIONDec 26, 16Jun 22, 17[G11C]
2017/0178,713 MEMORY REFRESH METHOD AND DEVICESDec 27, 16Jun 22, 17[G11C]
2017/0178,723 SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLSDec 28, 16Jun 22, 17[G11C]
2017/0178,726 RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODSDec 26, 16Jun 22, 17[G11C]
2017/0180,163 Methods and Circuits for Adaptive EqualizationJan 10, 17Jun 22, 17[H04L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9703483 Multiple memory rank system and selection method thereofNov 26, 13Jul 11, 17[G11C, G06F]
9703503 Reconfigurable memory system data strobesOct 08, 14Jul 11, 17[G11C, G06F]
9704560 Memory component with staggered power-down exitAug 19, 16Jul 11, 17[G11C, G06F]
9704576 Complementary RRAM applications for logic and ternary content addressable memory (TCAM)Feb 12, 15Jul 11, 17[G11C]
9705498 On-die terminationJun 21, 16Jul 11, 17[G11C, H03K]
9705710 High speed signaling system with adaptive transmit pre-emphasisJan 25, 16Jul 11, 17[H04L, H04B, H03K]
9697884 Variable width memory module supporting enhanced error detection and correctionSep 12, 16Jul 04, 17[G11C]
9698935 Variable code rate transmissionAug 09, 12Jul 04, 17[H04L, G06F]
9691447 Memory controller with staggered request signal outputSep 23, 15Jun 27, 17[G11C, G06F]
9691454 Memory controller with phase adjusted clock for performing memory operationsMay 20, 16Jun 27, 17[G11C, G06F]
9691504 DRAM retention test method for dynamic error correctionOct 19, 12Jun 27, 17[G11C, G06F]
9692431 Wide range frequency synthesizer with quadrature generation and spur cancellationJun 22, 15Jun 27, 17[H03L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2016/0308,693 PARTIAL RESPONSE RECEIVERABANApr 06, 16Oct 20, 16[H04L]
2016/0198,104 IMAGE SENSOR WITH A SPLIT-COUNTER ARCHITECTUREABANOct 07, 15Jul 07, 16[H04N, H01L]
2015/0349,798 CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FROM AN ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICEABANAug 11, 15Dec 03, 15[G06F, H03M]
2014/0314,406 Systems and Methods for Temperature Insensitive Photonic TransmissionABANNov 30, 12Oct 23, 14[H04J, H04B]
2014/0286,383 Selectable-tap EqualizerABANJan 01, 14Sep 25, 14[H04L, H04B]
2014/0219,008 Semiconductor Memory Device with Hierarchical BitlinesABANApr 04, 14Aug 07, 14[G11C]
2014/0098,589 REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUITABANSep 14, 12Apr 10, 14[G11C]
2014/0071,329 RECONFIGURABLE OPTICAL DEVICE USING A TOTAL INTERNAL REFLECTION (TIR) OPTICAL SWITCHABANSep 06, 13Mar 13, 14[H04N, G02B]
2014/0052,906 MEMORY CONTROLLER RESPONSIVE TO LATENCY-SENSITIVE APPLICATIONS AND MIXED-GRANULARITY ACCESS REQUESTSABANAug 05, 13Feb 20, 14[G11C, G06F]
2013/0346,822 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATIONABANJun 10, 13Dec 26, 13[H03M]
2013/0339,464 CONTACT AND IDENTITY MANAGEMENT IN A HETEROGENEOUS NETWORK WITH DISPARATE CLIENTSABANDec 13, 11Dec 19, 13[H04L]
2013/0322,510 SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTSABANMay 13, 13Dec 05, 13[H04B]
2013/0290,494 SESSION MANAGEMENT FOR COMMUNICATION IN A HETEROGENEOUS NETWORKABANOct 20, 11Oct 31, 13[H04L]
2013/0250,657 System and Method for Writing Data to an RRAM CellABANMar 07, 13Sep 26, 13[G11C]
2013/0168,674 Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated CircuitsABANDec 19, 12Jul 04, 13[H01L]
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTABANDec 22, 12Jun 13, 13[G11C]
2013/0148,447 Reducing Power Consumption in a Memory SystemABANDec 06, 12Jun 13, 13[G11C]
2013/0132,704 MEMORY CONTROLLER AND METHOD FOR TUNED ADDRESS MAPPINGABANAug 29, 11May 23, 13[G06F]
8442210 Signal line routing to reduce crosstalk effectsExpiredApr 06, 10May 14, 13[H04M]
8443223 Method and system for balancing receive-side supply loadExpiredJul 07, 09May 14, 13[H03K]

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