RAMBUS INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 623114
 
 
 
G11C STATIC STORES 50423
 
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 25596
 
 
 
H03K PULSE TECHNIQUE 18228
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 111241
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 9020
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 8785
 
 
 
H04B TRANSMISSION 77134
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 5324
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 5065

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2017/0372,769 MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMSJul 10, 17Dec 28, 17[G11C]
2017/0359,027 Digital Calibration for Multiphase OscillatorsJun 29, 17Dec 14, 17[H03B, H03L]
2017/0351,627 DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMPONENT FOR HIGH-PERFORMANCE, HIGH-CAPACITY REGISTERED MEMORY MODULESOct 28, 15Dec 07, 17[G06F]
2017/0344,275 MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORTDec 18, 15Nov 30, 17[G06F]
2017/0324,019 DIFFERENTIAL CRYOGENIC TRANSMITTERApr 04, 17Nov 09, 17[H01L]
2017/0315,953 MEMORY SYSTEM WITH INDEPENDENTLY ADJUSTABLE CORE AND INTERFACE DATA RATESJun 16, 17Nov 02, 17[G06F]
2017/0310,910 OVERSAMPLED IMAGE SENSOR WITH CONDITIONAL PIXEL READOUTMay 08, 17Oct 26, 17[H04N, H01L]
2017/0300,011 Systems and Methods for Improving Resolution in Lensless ImagingMar 14, 17Oct 19, 17[H04N, G03H]
2017/0293,552 SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICEApr 25, 17Oct 12, 17[G11C, G06F]
2017/0285,957 MULTIPLE MEMORY RANK SYSTEM AND SELECTION METHOD THEREOFJun 21, 17Oct 05, 17[G11C, G06F]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9864707 Time multiplexing at different rates to access different memory typesSep 26, 15Jan 09, 18[G06F]
9865329 Memory system topologies including a buffer device and an integrated circuit memory deviceDec 22, 16Jan 09, 18[G11C, G06F]
9858216 Coordinating memory operations using memory-device generated reference signalsJun 06, 16Jan 02, 18[G11C, G06F]
9859021 Timing-drift calibrationOct 15, 15Jan 02, 18[G01R, G01D, G11C, G06F, H03L]
9859899 Integrated circuit device having an injection-locked oscillatorJan 28, 16Jan 02, 18[H03B, H03K, H03L]
9860089 High-speed signaling systems and methods with adaptable, continuous-time equalizationJul 12, 16Jan 02, 18[H04L, H04B]
9851900 Multiple memory rank system and selection method thereofJun 21, 17Dec 26, 17[G11C, G06F]
9852105 Flash controller to provide a value that represents a parameter to a flash memoryAug 04, 16Dec 26, 17[G11C, G06F, H03K]
9847248 Method of making a stacked device assemblyMay 07, 14Dec 19, 17[H01L]
9841791 Circuit board assembly configurationDec 12, 14Dec 12, 17[G06F, H05K]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2017/0178,713 MEMORY REFRESH METHOD AND DEVICESABANDec 27, 16Jun 22, 17[G11C]
2017/0054,576 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer TimingABANSep 08, 16Feb 23, 17[H04L]
2016/0308,693 PARTIAL RESPONSE RECEIVERABANApr 06, 16Oct 20, 16[H04L]
2016/0198,104 IMAGE SENSOR WITH A SPLIT-COUNTER ARCHITECTUREABANOct 07, 15Jul 07, 16[H04N, H01L]
2016/0110,136 ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)ABANDec 18, 15Apr 21, 16[G06F]
2015/0349,798 CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FROM AN ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICEABANAug 11, 15Dec 03, 15[G06F, H03M]
2015/0331,732 MEMORY DEVICE HAVING STORAGE FOR AN ERROR CODE CORRECTION EVENT COUNTABANMay 08, 15Nov 19, 15[G11C, G06F]
2014/0314,406 Systems and Methods for Temperature Insensitive Photonic TransmissionABANNov 30, 12Oct 23, 14[H04J, H04B]
2014/0286,383 Selectable-tap EqualizerABANJan 01, 14Sep 25, 14[H04L, H04B]
2014/0219,008 Semiconductor Memory Device with Hierarchical BitlinesABANApr 04, 14Aug 07, 14[G11C]
2014/0098,589 REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUITABANSep 14, 12Apr 10, 14[G11C]
2014/0071,329 RECONFIGURABLE OPTICAL DEVICE USING A TOTAL INTERNAL REFLECTION (TIR) OPTICAL SWITCHABANSep 06, 13Mar 13, 14[H04N, G02B]
2014/0052,906 MEMORY CONTROLLER RESPONSIVE TO LATENCY-SENSITIVE APPLICATIONS AND MIXED-GRANULARITY ACCESS REQUESTSABANAug 05, 13Feb 20, 14[G11C, G06F]
2013/0346,822 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATIONABANJun 10, 13Dec 26, 13[H03M]
2013/0339,464 CONTACT AND IDENTITY MANAGEMENT IN A HETEROGENEOUS NETWORK WITH DISPARATE CLIENTSABANDec 13, 11Dec 19, 13[H04L]
2013/0322,510 SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTSABANMay 13, 13Dec 05, 13[H04B]
2013/0290,494 SESSION MANAGEMENT FOR COMMUNICATION IN A HETEROGENEOUS NETWORKABANOct 20, 11Oct 31, 13[H04L]
2013/0250,657 System and Method for Writing Data to an RRAM CellABANMar 07, 13Sep 26, 13[G11C]
2013/0168,674 Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated CircuitsABANDec 19, 12Jul 04, 13[H01L]
2013/0148,437 THERMAL ANNEAL USING WORD-LINE HEATING ELEMENTABANDec 22, 12Jun 13, 13[G11C]

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