RAMBUS INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 629115
 
  
 
G11C STATIC STORES 51523
 
  
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 260101
 
  
 
H03K PULSE TECHNIQUE 18430
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 114250
 
  
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 9321
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 8782
 
  
 
H04B TRANSMISSION 79133
 
  
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 5424
 
  
 
H04N PICTORIAL COMMUNICATION, e.g. TELEVISION 51191

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2018/0074,758 HIGH CAPACITY, HIGH PERFORMANCE MEMORY SYSTEMAug 29, 17Mar 15, 18[G06F]
2018/0076,987 EQUALIZING TRANSMITTER AND METHOD OF OPERATIONJul 25, 17Mar 15, 18[H04L]
2018/0047,436 MEMORY DEVICE COMPRISING PROGRAMMABLE COMMAND-AND-ADDRESS AND/OR DATA INTERFACESJun 14, 17Feb 15, 18[G11C, H01L]
2018/0011,805 Memory controller that uses a specific timing reference signal in connection with a data brust following a specified idle periodApr 26, 17Jan 11, 18[G11C, G06F]
2018/0013,438 INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATORJun 23, 17Jan 11, 18[H03K, H03L]
2017/0359,027 Digital Calibration for Multiphase OscillatorsJun 29, 17Dec 14, 17[H03B, H03L]
2017/0351,627 DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMPONENT FOR HIGH-PERFORMANCE, HIGH-CAPACITY REGISTERED MEMORY MODULESOct 28, 15Dec 07, 17[G06F]
2017/0344,275 MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORTDec 18, 15Nov 30, 17[G06F]
2017/0324,019 DIFFERENTIAL CRYOGENIC TRANSMITTERApr 04, 17Nov 09, 17[H01L]
2017/0315,953 MEMORY SYSTEM WITH INDEPENDENTLY ADJUSTABLE CORE AND INTERFACE DATA RATESJun 16, 17Nov 02, 17[G06F]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9921751 Methods and systems for mapping a peripheral function onto a legacy memory interfaceJan 19, 16Mar 20, 18[G11C, G06F]
9923602 Configurable, power supply voltage referenced single-ended signaling with ESD protectionApr 25, 16Mar 20, 18[H04L, H02H, G06F, H04B]
9923711 Low power edge and data samplingApr 13, 11Mar 20, 18[H04L]
9916196 Memory module with dedicated repair devicesFeb 25, 15Mar 13, 18[G11C, G06F]
9916873 Extended capacity memory module with dynamic data buffersFeb 02, 16Mar 13, 18[G11C]
9916877 Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory dieNov 30, 15Mar 13, 18[G11C, H01L]
9917708 Partial response receiverApr 06, 16Mar 13, 18[H04L, H01L]
9910612 Memory buffer with one or more auxiliary interfacesApr 25, 16Mar 06, 18[G11C, G06F]
9911468 Memory with deferred fractional row activationDec 26, 16Mar 06, 18[G11C]
9912469 Phase control block for managing multiple clock domains in systems with frequency offsetsDec 05, 16Mar 06, 18[H04L, H03L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2017/0178,713 MEMORY REFRESH METHOD AND DEVICESABANDec 27, 16Jun 22, 17[G11C]
2017/0132,150 Memory Controller For Selective Rank Or Subrank AccessABANOct 17, 16May 11, 17[G06F]
2017/0054,576 Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer TimingABANSep 08, 16Feb 23, 17[H04L]
2016/0198,104 IMAGE SENSOR WITH A SPLIT-COUNTER ARCHITECTUREABANOct 07, 15Jul 07, 16[H04N, H01L]
2016/0110,136 ISOLATED SHARED MEMORY ARCHITECTURE (iSMA)ABANDec 18, 15Apr 21, 16[G06F]
2015/0349,798 CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FROM AN ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICEABANAug 11, 15Dec 03, 15[G06F, H03M]
2015/0331,732 MEMORY DEVICE HAVING STORAGE FOR AN ERROR CODE CORRECTION EVENT COUNTABANMay 08, 15Nov 19, 15[G11C, G06F]
2014/0314,406 Systems and Methods for Temperature Insensitive Photonic TransmissionABANNov 30, 12Oct 23, 14[H04J, H04B]
2014/0286,383 Selectable-tap EqualizerABANJan 01, 14Sep 25, 14[H04L, H04B]
2014/0219,008 Semiconductor Memory Device with Hierarchical BitlinesABANApr 04, 14Aug 07, 14[G11C]
2014/0098,589 REPLACEMENT OF A FAULTY MEMORY CELL WITH A SPARE CELL FOR A MEMORY CIRCUITABANSep 14, 12Apr 10, 14[G11C]
2014/0071,329 RECONFIGURABLE OPTICAL DEVICE USING A TOTAL INTERNAL REFLECTION (TIR) OPTICAL SWITCHABANSep 06, 13Mar 13, 14[H04N, G02B]
2014/0052,906 MEMORY CONTROLLER RESPONSIVE TO LATENCY-SENSITIVE APPLICATIONS AND MIXED-GRANULARITY ACCESS REQUESTSABANAug 05, 13Feb 20, 14[G11C, G06F]
2013/0346,822 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATIONABANJun 10, 13Dec 26, 13[H03M]
2013/0339,464 CONTACT AND IDENTITY MANAGEMENT IN A HETEROGENEOUS NETWORK WITH DISPARATE CLIENTSABANDec 13, 11Dec 19, 13[H04L]
2013/0322,510 SIGNAL LINE ROUTING TO REDUCE CROSSTALK EFFECTSABANMay 13, 13Dec 05, 13[H04B]
2013/0290,494 SESSION MANAGEMENT FOR COMMUNICATION IN A HETEROGENEOUS NETWORKABANOct 20, 11Oct 31, 13[H04L]
2013/0250,657 System and Method for Writing Data to an RRAM CellABANMar 07, 13Sep 26, 13[G11C]
8509321 Simultaneous bi-directional linkExpiredDec 23, 04Aug 13, 13[H04K]
8497544 Repairing defects in a nonvolatile semiconductor memory module utilizing a heating elementExpiredJun 01, 12Jul 30, 13[H01L]

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