SAIFUN SEMICONDUCTORS LTD.
Patent Owner
Stats
- 100 US PATENTS IN FORCE
- 0 US APPLICATIONS PENDING
- Oct 12, 2010 most recent publication
Details
- 100 Issued Patents
- 0 Issued in last 3 years
- 0 Published in last 3 years
- 6,507 Total Citation Count
- Jul 23, 1996 Earliest Filing
- 33 Expired/Abandoned/Withdrawn Patents
Patent Activity in the Last 10 Years
Technologies
Intl Class
Technology
Matters
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Top Patents (by citation)
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Recent Publications
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Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
7811887 Forming silicon trench isolation (STI) in semiconductor devices self-aligned to diffusionNov 01, 07Oct 12, 10[H01L]
7755938 Method for reading a memory array with neighbor effect cancellationApr 19, 04Jul 13, 10[G11C]
7692961 Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injectionAug 02, 06Apr 06, 10[G11C]
7675782 Method, system and circuit for programming a non-volatile memory arrayOct 17, 06Mar 09, 10[G11C]
Expired/Abandoned/Withdrawn Patents
Patent #
Title
Status
Filing Date
Issue/Pub Date
Intl Class
2009/0129,166 METHOD, CIRCUIT AND SYSTEM FOR SENSING A CELL IN A NON-VOLATILE MEMORY ARRAYAbandonedNov 15, 07May 21, 09[G11C]
2009/0065,841 SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLSAbandonedSep 06, 07Mar 12, 09[H01L]
2009/0032,862 Non-volatile memory cell and non-volatile memory device using said cellAbandonedOct 31, 07Feb 05, 09[H01L]
2008/0192,544 Error correction coding techniques for non-volatile memoryAbandonedFeb 12, 08Aug 14, 08[G11C]
2008/0111,177 Non-volatile memory cell and non-volatile memory device using said cellAbandonedDec 31, 07May 15, 08[H01L]
2008/0111,182 Forming buried contact etch stop layer (CESL) in semiconductor devices self-aligned to diffusionAbandonedNov 01, 07May 15, 08[H01L]
2008/0109,594 Non-volatile memory device controlled by a micro-controllerAbandonedOct 31, 07May 08, 08[G06F]
2007/0255,889 Non-volatile memory device and method of operating the deviceAbandonedMar 22, 07Nov 01, 07[G06F]
2007/0211,551 Method for dynamic performance optimization conforming to a dynamic maximum current levelAbandonedNov 24, 06Sep 13, 07[G11C]
2007/0177,428 Memory circuit arrangement and method for reading and/or verifying the status of memory cells of a memory cell arrayAbandonedJan 30, 06Aug 02, 07[G11C]
2007/0173,017 Advanced non-volatile memory array and method of fabrication thereofAbandonedJan 20, 06Jul 26, 07[H01L]
2007/0087,503 Improving NROM device characteristics using adjusted gate work functionAbandonedOct 17, 05Apr 19, 07[H01L]
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