SANDISK 3D LLC

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 41985
 
 
 
G11C STATIC STORES 30627
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 30350
 
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 1080
 
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 891
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 663
 
 
 
B82Y SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE  OR TREATMENT OF NANO-STRUCTURES435
 
 
 
C23C COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL 282
 
 
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 2169
 
 
 
H02M APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF 274

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0252,298 METHODS AND APPARATUS FOR METAL OXIDE REVERSIBLE RESISTANCE-SWITCHING MEMORY DEVICESMar 10, 13Sep 11, 14[H01L]
2014/0252,454 VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATIONMar 07, 13Sep 11, 14[H01L]
2014/0254,231 3D Non-Volatile Memory Having Low-Current Cells and MethodsMar 04, 14Sep 11, 14[G11C, H01L]
2014/0254,242 NON-VOLATILE STORAGE SYSTEM BIASING CONDITIONS FOR STANDBY AND FIRST READMar 04, 14Sep 11, 14[G11C]
2014/0247,676 Charge Pump with a Power-Controlled Clock Buffer to Reduce Power Consumption and Output Voltage RippleApr 22, 14Sep 04, 14[G11C]
2014/0248,763 Vertical Bit Line Non-Volatile Memory Systems And Methods Of FabricationMar 04, 14Sep 04, 14[H01L]
2014/0250,260 ASYNCHRONOUS FIFO BUFFER FOR MEMORY ACCESSFeb 28, 14Sep 04, 14[G06F]
2014/0239,248 THREE-DIMENSIONAL NONVOLATILE MEMORY AND METHOD OF FABRICATIONMay 06, 14Aug 28, 14[H01L]
2014/0241,031 DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAMEFeb 28, 13Aug 28, 14[G11C, H01L]
2014/0241,035 RERAM FORMING WITH RESET AND ILOAD COMPENSATIONFeb 28, 13Aug 28, 14[G11C]
2014/0241,090 SMART READ SCHEME FOR MEMORY ARRAY SENSINGFeb 22, 13Aug 28, 14[G11C]
2014/0242,764 THREE DIMENSIONAL NON-VOLATILE STORAGE WITH ASYMMETRICAL VERTICAL SELECT DEVICESMay 03, 14Aug 28, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,824,183 Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereofDec 12, 11Sep 02, 14[G11C]
8,824,191 Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereofAug 22, 13Sep 02, 14[G11C]
8,816,315 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the sameFeb 11, 13Aug 26, 14[H01L]
8,817,514 Non-volatile memory having 3D array of read/write elements with low current structures and methods thereofJan 07, 14Aug 26, 14[G11C]
8,817,524 Resistive random access memory cells having metal alloy current limiting layersDec 20, 12Aug 26, 14[G11C, H01L]
8,809,114 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the sameAug 12, 13Aug 19, 14[H01L]
8,809,128 Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterningOct 26, 10Aug 19, 14[H01L]
8,809,159 Radiation enhanced resistive switching layersDec 20, 12Aug 19, 14[H01L]
8,809,205 Sequential atomic layer deposition of electrodes and resistive switching componentsDec 20, 12Aug 19, 14[H01L]
8,802,492 Method for forming resistive switching memory elementsAug 29, 11Aug 12, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0314,971 METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGENov 16, 12Nov 28, 13[G11C, H01L]
2012/0223,414 METHODS FOR INCREASING BOTTOM ELECTRODE PERFORMANCE IN CARBON-BASED MEMORY DEVICESAug 08, 11Sep 06, 12[H01L, B82Y]
2012/0091,418 BIPOLAR STORAGE ELEMENTS FOR USE IN MEMORY CELLS AND METHODS OF FORMING THE SAMEOct 14, 10Apr 19, 12[H01L]
2011/0278,529 MEMORY EMPLOYING DIAMOND-LIKE CARBON RESISTIVITY-SWITCHABLE MATERIAL AND METHODS OF FORMING THE SAMEMay 14, 10Nov 17, 11[H01L]
2011/0210,306 MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAMEFeb 26, 10Sep 01, 11[H01L]
2011/0186,799 NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOFFeb 03, 11Aug 04, 11[H01L, B82Y]
2011/0156,044 DENSE ARRAYS AND CHARGE STORAGE DEVICESFeb 14, 11Jun 30, 11[H01L]
2010/0301,449 METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHYAug 13, 10Dec 02, 10[B29C, H01L]
2010/0283,053 NONVOLATILE MEMORY ARRAY COMPRISING SILICON-BASED DIODES FABRICATED AT LOW TEMPERATUREMay 11, 09Nov 11, 10[H01L]
2010/0078,758 MIIM DIODESSep 29, 08Apr 01, 10[G11C, H01L]
2010/0032,640 MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAMEAug 05, 09Feb 11, 10[H01L]
2010/0012,914 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAMEJul 17, 09Jan 21, 10[H01L]
2010/0006,812 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAMEJul 08, 09Jan 14, 10[H01L]
2009/0327,535 ADJUSTABLE READ LATENCY FOR MEMORY DEVICE IN PAGE-MODE ACCESSJun 30, 08Dec 31, 09[G06F]
2009/0282,267 PARTIAL SCRAMBLING TO REDUCE CORRELATIONJun 30, 08Nov 12, 09[H04L]
2009/0273,022 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCHJul 14, 09Nov 05, 09[H01L]
2009/0166,610 MEMORY CELL WITH PLANARIZED CARBON NANOTUBE LAYER AND METHODS OF FORMING THE SAMEDec 31, 07Jul 02, 09[H01L]
2009/0104,756 METHOD TO FORM A REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTIVITY-SWITCHING GROWN OXIDEJun 29, 07Apr 23, 09[H01L]
2009/0086,521 MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAMESep 28, 07Apr 02, 09[G11C, H01L]
2009/0087,993 METHODS AND APPARATUS FOR COST-EFFECTIVELY INCREASING FEATURE DENSITY USING A MASK SHRINKING PROCESS WITH DOUBLE PATTERNINGSep 28, 07Apr 02, 09[H01L]

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