SANDISK 3D LLC

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Technologies

Intl Class Technology # of Patents Rank
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 25791
 
 
 
G11C STATIC STORES 22432
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 28272
 
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 1076
 
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 877
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 565
 
 
 
C23C COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL 261
 
 
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 2139
 
 
 
H02M APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF 259
 
 
 
B05D PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL 167

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
6,034,882 Vertically stacked field programmable nonvolatile memory and method of fabricationNov 16, 98Mar 07, 00[G11C]735
6,185,122 Vertically stacked field programmable nonvolatile memory and method of fabricationDec 22, 99Feb 06, 01[G11C]458
6,420,215 Three-dimensional memory array and method of fabricationMar 21, 01Jul 16, 02[H01L]439
6,483,736 Vertically stacked field programmable nonvolatile memory and method of fabricationAug 24, 01Nov 19, 02[G11C]248
6,351,406 Vertically stacked field programmable nonvolatile memory and method of fabricationNov 15, 00Feb 26, 02[G11C]242
6,888,750 Nonvolatile memory on SOI and compound semiconductor substrates and method of fabricationAug 13, 01May 03, 05[G11C]239
6,627,530 Patterning three dimensional structuresDec 22, 00Sep 30, 03[H01L]207
6,525,953 Vertically-stacked, field-programmable, nonvolatile memory and method of fabricationAug 13, 01Feb 25, 03[G11C]184
6,952,030 High-density three-dimensional memory cellMay 26, 04Oct 04, 05[H01L]155
6,881,994 Monolithic three dimensional array of charge storage devices containing a planarized surfaceAug 13, 01Apr 19, 05[H01L]145

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0094,278 Non-Volatile Memory Cell Containing an In-Cell ResistorJul 18, 12Apr 18, 13[G11C, H01L]
2013/0075,685 METHODS AND APPARATUS FOR INCLUDING AN AIR GAP IN CARBON-BASED MEMORY DEVICESSep 22, 11Mar 28, 13[H01L, B82Y]
2013/0021,837 CROSS POINT NON-VOLATILE MEMORY CELLAug 21, 12Jan 24, 13[G11C]
2013/0023,085 METHOD FOR FORMING METAL OXIDES AND SILICIDES IN A MEMORY DEVICEJul 22, 11Jan 24, 13[H01L]
2013/0010,523 MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEMEAug 31, 12Jan 10, 13[G11C]
2013/0003,440 Single Device Driver Circuit to Control Three-Dimensional Memory Element ArraySep 10, 12Jan 03, 13[G11C, H01L]
2012/0302,029 PUNCH-THROUGH DIODE STEERING ELEMENTAug 09, 12Nov 29, 12[H01L]
2012/0280,201 OPTIMIZED ELECTRODES FOR RE-RAMJul 19, 12Nov 08, 12[H01L]
2012/0275,210 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMINGApr 27, 11Nov 01, 12[G11C]
2012/0276,744 Patterning Method for High Density Pillar StructuresMay 03, 12Nov 01, 12[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,435,831 Non-volatile storage with metal oxide switching element and methods for fabricating the sameNov 09, 10May 07, 13[H01L]
8,436,447 Memory cell that includes a carbon-based memory element and methods of forming the sameApr 23, 10May 07, 13[H01L]
8,431,417 Methods for increasing carbon nano-tube (CNT) yield in memory devicesAug 18, 09Apr 30, 13[H01L]
8,431,492 Memory cell that includes a sidewall collar for pillar isolation and methods of forming the sameFeb 02, 10Apr 30, 13[H01L]
8,427,858 Large array of upward pointinig p-i-n diodes having large and uniform currentNov 11, 11Apr 23, 13[G11C]
8,427,890 Program cycle skipJun 05, 12Apr 23, 13[G11C]
8,421,050 Electronic devices including carbon nano-tube films having carbon-based liners, and methods of forming the sameOct 29, 09Apr 16, 13[H01L]
8,410,582 3D polysilicon diode with low contact resistance and method for forming sameMay 23, 12Apr 02, 13[H01L]
8,395,926 Memory cell with resistance-switching layers and lateral arrangementJun 09, 11Mar 12, 13[G11C]
8,395,927 Memory cell with resistance-switching layers including breakdown layerJun 09, 11Mar 12, 13[G11C]

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Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
Scheuerlein Roy E
Cupertino, CA
270
Herner S Brad
San Jose, CA
131
Petti Christopher J
Mountain View, CA
84
Kumar Tanmay
Pleasanton, CA
82
Fasoli Luca G
San Jose, CA
67
Cleeves James M
Redwood City, CA
62
Scheuerlein Roy E.
Not Provided
56
Fasoli Luca
San Jose, CA
55
Chen Yung-Tin
Santa Clara, CA
53
Radigan Steven J
Fremont, CA
52