SANDISK 3D LLC

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 37686
 
 
 
G11C STATIC STORES 27728
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 29337
 
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 1177
 
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 883
 
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 564
 
 
 
B82Y SPECIFIC USES OR APPLICATIONS OF NANO-STRUCTURES; MEASUREMENT OR ANALYSIS OF NANO-STRUCTURES; MANUFACTURE  OR TREATMENT OF NANO-STRUCTURES435
 
 
 
C23C COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL 281
 
 
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 2161
 
 
 
H02M APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF 272

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0198,558 Non-Volatile Storage System Using Opposite Polarity Programming Signals For MIM Memory CellMar 17, 14Jul 17, 14[G11C]
2014/0192,585 Resistive Random Access Memory Cell Having Three or More Resistive StatesJan 10, 13Jul 10, 14[G11C, H01L]
2014/0192,586 Resistive Random Access Memory Cells Having Variable Switching CharacteristicsJan 10, 13Jul 10, 14[G11C, H01L]
2014/0192,595 Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line ArchitectureJan 13, 14Jul 10, 14[G11C]
2014/0183,436 Nonvolatile Memory Device Having a Current Limiting ElementFeb 21, 14Jul 03, 14[H01L]
2014/0185,351 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMINGMar 09, 14Jul 03, 14[G11C]
2014/0175,354 SEQUENTIAL ATOMIC LAYER DEPOSITION OF ELECTRODES AND RESISTIVE SWITCHING COMPONENTSDec 20, 12Jun 26, 14[H01L]
2014/0175,355 Carbon Doped Resistive Switching LayersDec 20, 12Jun 26, 14[H01L]
2014/0175,356 Resistive Random Access Memory Access Cells Having Thermally Isolating StructuresDec 20, 12Jun 26, 14[H01L]
2014/0175,357 Morphology control of ultra-thin MeOx layerDec 21, 12Jun 26, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,787,066 Method for forming resistive switching memory elements with improved switching behaviorOct 26, 11Jul 22, 14[G11C]
8,779,407 Multifunctional electrodeFeb 07, 12Jul 15, 14[H01L]
8,780,605 Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architectureJan 07, 13Jul 15, 14[G11C]
8,780,651 Continuous programming of non-volatile memoryJun 28, 12Jul 15, 14[G11C]
8,772,749 Bottom electrodes for use with metal oxide resistivity switching layersMar 14, 11Jul 08, 14[H01L]
8,773,898 Methods and apparatus for reducing programming time of a memory cellMay 09, 13Jul 08, 14[G11C]
8,766,332 Optimization of critical dimensions and pitch of patterned features in and above a substrateSep 13, 12Jul 01, 14[H01L]
8,766,414 Deposited semiconductor structure to minimize N-type dopant diffusion and method of makingNov 16, 12Jul 01, 14[H01L]
8,759,176 Patterning of submicron pillars in a memory arrayApr 10, 09Jun 24, 14[H01L]
8,755,223 Three dimensional non-volatile storage with asymmetrical vertical select devicesDec 12, 11Jun 17, 14[G11C]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0314,971 METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGENov 16, 12Nov 28, 13[G11C, H01L]
2012/0223,414 METHODS FOR INCREASING BOTTOM ELECTRODE PERFORMANCE IN CARBON-BASED MEMORY DEVICESAug 08, 11Sep 06, 12[H01L, B82Y]
2011/0278,529 MEMORY EMPLOYING DIAMOND-LIKE CARBON RESISTIVITY-SWITCHABLE MATERIAL AND METHODS OF FORMING THE SAMEMay 14, 10Nov 17, 11[H01L]
2011/0210,306 MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAMEFeb 26, 10Sep 01, 11[H01L]
2011/0186,799 NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOFFeb 03, 11Aug 04, 11[H01L, B82Y]
2011/0156,044 DENSE ARRAYS AND CHARGE STORAGE DEVICESFeb 14, 11Jun 30, 11[H01L]
2010/0301,449 METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHYAug 13, 10Dec 02, 10[B29C, H01L]
2010/0283,053 NONVOLATILE MEMORY ARRAY COMPRISING SILICON-BASED DIODES FABRICATED AT LOW TEMPERATUREMay 11, 09Nov 11, 10[H01L]
2010/0078,758 MIIM DIODESSep 29, 08Apr 01, 10[G11C, H01L]
2010/0032,640 MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAMEAug 05, 09Feb 11, 10[H01L]
2010/0012,914 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAMEJul 17, 09Jan 21, 10[H01L]
2010/0006,812 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAMEJul 08, 09Jan 14, 10[H01L]
2009/0327,535 ADJUSTABLE READ LATENCY FOR MEMORY DEVICE IN PAGE-MODE ACCESSJun 30, 08Dec 31, 09[G06F]
2009/0282,267 PARTIAL SCRAMBLING TO REDUCE CORRELATIONJun 30, 08Nov 12, 09[H04L]
2009/0273,022 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCHJul 14, 09Nov 05, 09[H01L]
2009/0166,610 MEMORY CELL WITH PLANARIZED CARBON NANOTUBE LAYER AND METHODS OF FORMING THE SAMEDec 31, 07Jul 02, 09[H01L]
2009/0104,756 METHOD TO FORM A REWRITEABLE MEMORY CELL COMPRISING A DIODE AND A RESISTIVITY-SWITCHING GROWN OXIDEJun 29, 07Apr 23, 09[H01L]
2009/0086,521 MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAMESep 28, 07Apr 02, 09[G11C, H01L]
2009/0087,993 METHODS AND APPARATUS FOR COST-EFFECTIVELY INCREASING FEATURE DENSITY USING A MASK SHRINKING PROCESS WITH DOUBLE PATTERNINGSep 28, 07Apr 02, 09[H01L]
2009/0003,083 Memory cell with voltage modulated sidewall poly resistorJun 28, 07Jan 01, 09[G11C]

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