SPANSION LLC

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Technologies

Intl Class Technology # of Patents Rank
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 1004 30
 
 
G11C STATIC STORES 683 14
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 110 195
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 38 90
 
 
G05F SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES 12 73
 
 
H03K PULSE TECHNIQUE 12 94
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 11 157
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 5 81
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 5 91
 
 
G01N INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES 3 135
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Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
6,639,849 Nonvolatile semiconductor memory device programming second dynamic reference cell according to threshold value of first dynamic reference cell Feb 03, 03 Oct 28, 03 [G11C] 245
6,674,138 Use of high-k dielectric materials in modified ONO structure for semiconductor devices Dec 31, 01 Jan 06, 04 [H01L] 194
5,991,202 Method for reducing program disturb during self-boosting in a NAND flash memory Sep 24, 98 Nov 23, 99 [G11C] 193
5,712,815 Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells Apr 22, 96 Jan 27, 98 [G11C] 191
6,215,702 Method of maintaining constant erasing speeds for non-volatile memory cells Feb 16, 00 Apr 10, 01 [G11C] 164
5,477,499 Memory architecture for a three volt flash EEPROM Oct 13, 93 Dec 19, 95 [G11C] 164
5,995,417 Scheme for page erase and erase verify in a non-volatile memory array Oct 20, 98 Nov 30, 99 [G11C] 158
5,754,475 Bit line discharge method for reading a multiple bits-per-cell flash EEPROM Jun 27, 97 May 19, 98 [G11C] 155
6,222,768 Auto adjusting window placement scheme for an NROM virtual ground array Apr 26, 00 Apr 24, 01 [G11C] 150
6,642,573 Use of high-K dielectric material in modified ONO structure for semiconductor devices Mar 13, 02 Nov 04, 03 [H01L] 148
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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0105,878 FLASH MEMORY CELL WITH FLAIR GATE Dec 21, 12 May 02, 13 [H01L]
2013/0107,644 STORAGE DEVICE, CONTROL METHOD OF STORAGE DEVICE, AND CONTROL METHOD OF STORAGE CONTROL DEVICE Dec 21, 12 May 02, 13 [G11C]
2013/0100,318 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFORE Dec 11, 12 Apr 25, 13 [G06F, H01L]
2013/0094,297 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME Dec 03, 12 Apr 18, 13 [G11C]
2013/0083,604 APPARATUS AND METHOD FOR SMART VCC TRIP POINT DESIGN FOR TESTABILITY Sep 29, 11 Apr 04, 13 [G11C, H03L]
2013/0078,795 ETCH STOP LAYER FOR MEMORY CELL RELIABILITY IMPROVEMENT Sep 14, 12 Mar 28, 13 [H01L]
2013/0067,153 HARDWARE BASED WEAR LEVELING MECHANISM Nov 07, 12 Mar 14, 13 [G06F]
2013/0060,980 VARIABLE READ LATENCY ON A SERIAL MEMORY BUS Nov 05, 12 Mar 07, 13 [G06F]
2013/0032,725 IMAGING DEVICE Jul 24, 12 Feb 07, 13 [G01T]
2013/0023,101 METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY SPACERS FOR CORE AND HIGH VOLTAGE DEVICES AND LOW TEMPERATURE SPACERS FOR HIGH PERFORMANCE LOGIC DEVICES Jul 18, 11 Jan 24, 13 [H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,436,289 System and method for detecting particles with a semiconductor device Jul 28, 10 May 07, 13 [H01L]
8,438,460 Error correction scheme for non-volatile memory Jun 22, 12 May 07, 13 [H03M]
8,421,241 System and method for stacking a plurality of electrically coupled semiconductor chips with a conductive pin Oct 27, 08 Apr 16, 13 [H01L]
8,422,668 Table lookup operation on masked data Dec 15, 06 Apr 16, 13 [G06F]
8,423,705 Semiconductor device and method for controlling thereof Jun 13, 08 Apr 16, 13 [G06F]
8,415,734 Memory device protection layer Dec 07, 06 Apr 09, 13 [H01L]
8,417,874 High speed memory having a programmable read preamble Jan 21, 10 Apr 09, 13 [G06F]
8,409,952 Method of forming an electronic device including forming a charge storage element in a trench of a workpiece Apr 14, 08 Apr 02, 13 [H01L]
8,409,994 Gate trim process using either wet etch or dry etch approach to target CD for selected transistors Oct 21, 11 Apr 02, 13 [H01L]
8,404,541 Strapping contact for charge protection May 28, 10 Mar 26, 13 [H01L]

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Top Inventors for This Owner

Inventor Name Address Patent #
Ramsbey Mark T
Sunnyvale, US
107
Sun Yu
Saratoga, US
93
Chang Kuo-Tung
Saratoga, US
91
Yang Nian
Mountain View, US
87
Hui Angela T
Fremont, US
86
Chang Chi
Saratoga, US
79
Kinoshita Hiroyuki
San Jose, US
75
Ngo Minh Van
Fremont, US
74
Shiraiwa Hidehiko
San Jose, US
71
Zheng Wei
Sunnyvale, US
69
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