STATS CHIPPAC LTD.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 134127
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 28104
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1051
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 7115
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 671
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 5131
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4147
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 467
 
 
 
B29C SHAPING OR JOINING OF PLASTICS; SHAPING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL; AFTER- TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING 294
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 251

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0183,718 Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale PackagesSep 25, 13Jul 03, 14[H01L]
2014/0183,761 Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale PackagesNov 02, 13Jul 03, 14[H01L]
2014/0175,623 Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor DieMar 01, 14Jun 26, 14[H01L]
2014/0175,639 Semiconductor Device and Method of Simultaneous Molding and Thermalcompression BondingSep 26, 13Jun 26, 14[H01L]
2014/0175,640 Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer FormSep 27, 13Jun 26, 14[H01L]
2014/0175,642 Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection PropertiesFeb 27, 14Jun 26, 14[H01L]
2014/0175,661 Semiconductor Device and Method of Making Bumpless Flipchip Interconnect StructuresSep 27, 13Jun 26, 14[H01L]
2014/0159,236 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingFeb 14, 14Jun 12, 14[H01L]
2014/0159,251 Semiconductor Device and Method of Forming Low Profile Fan-Out Package with Vertical Interconnection UnitsSep 26, 13Jun 12, 14[H01L]
2014/0145,340 Flip Chip Interconnection StructureJan 31, 14May 29, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,779,562 Integrated circuit packaging system with interposer shield and method of manufacture thereofMar 24, 11Jul 15, 14[H01L]
8,779,565 Integrated circuit mounting system with paddle interlock and method of manufacture thereofDec 14, 10Jul 15, 14[H01L]
8,779,568 Integrated circuit package system with encapsulation lockJan 06, 12Jul 15, 14[H01L]
8,779,570 Stackable integrated circuit package systemMar 19, 08Jul 15, 14[H01L]
8,772,916 Integrated circuit package system employing mold flash prevention technologyJun 28, 12Jul 08, 14[H01L]
8,765,525 Method of manufacturing an integrated circuit packaging system including lasering through encapsulant over interposerJun 16, 11Jul 01, 14[H01L]
8,766,426 Integrated circuit packaging system with warpage control and method of manufacture thereofSep 24, 10Jul 01, 14[H01L]
8,766,428 Integrated circuit packaging system with flip chip and method of manufacture thereofDec 02, 09Jul 01, 14[H01L]
8,759,155 Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress reliefMar 01, 13Jun 24, 14[H01L]
8,759,159 Integrated circuit packaging system with electrical interface and method of manufacture thereofMay 05, 11Jun 24, 14[H01L]
8,759,209 Semiconductor device and method of forming a dual UBM structure for lead free bump connectionsFeb 17, 11Jun 24, 14[H01L]
8,759,954 Integrated circuit package system with offset stacked dieAug 03, 11Jun 24, 14[H01L]
8,759,972 Semiconductor device and method of forming composite bump-on-lead interconnectionNov 29, 11Jun 24, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFMar 23, 10May 12, 11[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFJun 19, 09Dec 23, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFNov 20, 08May 20, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESMar 26, 08Oct 01, 09[H01L]
2009/0236,723 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-IN-PACKAGE AND METHOD OF MANUFACTURE THEREOFMar 13, 09Sep 24, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPDec 17, 07Jun 18, 09[H01L]
2009/0127,715 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTRUSIONNov 15, 07May 21, 09[H01L]
2009/0001,549 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SYMMETRIC PACKAGINGJun 29, 07Jan 01, 09[H01L]
2008/0315,374 INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH MAGNETIC FILMJun 25, 07Dec 25, 08[H01L]
2008/0308,933 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT CONNECTION STRUCTURESJun 14, 07Dec 18, 08[H01L]
2008/0251,901 STACKED INTEGRATED CIRCUIT PACKAGE SYSTEMApr 28, 08Oct 16, 08[H01L]
2008/0237,157 WAFER TRANSPORT SYSTEMMar 30, 07Oct 02, 08[H01L]
2008/0185,737 INTEGRATED CIRCUIT SYSTEM WITH PRE-CONFIGURED BOND WIRE BALLFeb 01, 08Aug 07, 08[B23K, H01L]

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Top Inventors for This Owner

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