STATS CHIPPAC LTD.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 169183
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 7135
 
 
 
B81C PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS 224
 
 
 
B81B MICRO-STRUCTURAL DEVICES OR SYSTEMS, e.g. MICRO-MECHANICAL DEVICES 128
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 1124

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0141,238 Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLB-MLP)Jan 27, 16May 19, 16[H01L]
2016/0118,332 Semiconductor Device and Method of Fabricating 3D Package With Short Cycle Time and High YieldOct 20, 15Apr 28, 16[H01L]
2016/0118,333 Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High YieldDec 16, 15Apr 28, 16[H01L]
2016/0111,410 Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical InterconnectDec 16, 15Apr 21, 16[H01L]
2016/0104,681 Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor DieDec 18, 15Apr 14, 16[H01L]
2016/0104,731 Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity RegionDec 18, 15Apr 14, 16[B81C, H01L]
2016/0071,813 Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder MaskNov 09, 15Mar 10, 16[H01L]
2016/0043,047 Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level PackageJul 31, 15Feb 11, 16[H01L]
2016/0013,148 Semiconductor Device and Method of Forming Wafer-Level Interconnect Structures with Advanced Dielectric CharacteristicsSep 22, 15Jan 14, 16[H01L]
2015/0380,310 Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic PassivationJun 26, 14Dec 31, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,343,429 Semiconductor device and method of forming double-sided through vias in saw streetsJan 06, 10May 17, 16[H01L]
9,330,945 Integrated circuit package system with multi-chip moduleSep 18, 07May 03, 16[H01L]
9,330,994 Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuringMar 28, 14May 03, 16[H01L]
9,331,003 Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereofMar 28, 14May 03, 16[H01L]
9,324,584 Integrated circuit packaging system with transferable trace lead frameDec 14, 12Apr 26, 16[H01L]
9,324,641 Integrated circuit packaging system with external interconnect and method of manufacture thereofMar 20, 12Apr 26, 16[H01L]
9,324,673 Integrated circuit packaging system with wafer level reconfiguration and method of manufacture thereofJun 23, 11Apr 26, 16[H01L]
9,324,700 Semiconductor device and method of forming shielding layer over integrated passive device using conductive channelsSep 05, 08Apr 26, 16[H01L]
9,318,403 Integrated circuit packaging system with magnetic film and method of manufacture thereofAug 16, 11Apr 19, 16[H01L]
9,312,194 Integrated circuit packaging system with terminals and method of manufacture thereofMar 20, 12Apr 12, 16[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
8,900,920 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerWithdrawnAug 11, 11Dec 02, 14[H01L, H05K]
2012/0211,881 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump ProcessABANApr 20, 10Aug 23, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFABANJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFABANJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFABANMar 23, 10May 12, 11[H01L]
2011/0062,599 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANSep 17, 09Mar 17, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateABANJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFABANJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFABANDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFABANNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSABANSep 26, 08Apr 01, 10[H01L]
2009/0283,889 INTEGRATED CIRCUIT PACKAGE SYSTEMABANMay 16, 08Nov 19, 09[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESABANMar 26, 08Oct 01, 09[H01L]
2009/0243,069 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTIONABANMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingABANMar 12, 08Sep 17, 09[H01L]
2009/0212,441 Semiconductor Interconnect Structure with Stacked Vias Separated by Signal Line and Method ThereforABANFeb 22, 08Aug 27, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESABANJan 30, 08Jul 30, 09[H01L]

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