STATS CHIPPAC LTD.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 149027
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3499
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1252
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 8113
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 673
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 5140
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4146
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 367
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 348
 
 
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 2170

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0021,754 Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal ManagementOct 08, 14Jan 22, 15[H01L]
2015/0008,597 Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During SingulationSep 23, 14Jan 08, 15[H01L]
2015/0001,703 Semiconductor Device and Method of Individual Die Bonding Followed by Simultaneous Multiple Die Thermal Compression BondingJun 27, 13Jan 01, 15[H01L]
2015/0001,705 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED PAD ON LAYERED SUBSTRATE AND METHOD OF MANUFACTURE THEREOFJun 27, 13Jan 01, 15[H01L]
2015/0001,707 Semiconductor Device and Method of Using Substrate With Conductive Posts and Protective Layers to Form Embedded Sensor Die PackageJun 28, 13Jan 01, 15[H01L]
2015/0001,708 Semiconductor Device and Method of Forming Low Profile 3D Fan-Out PackageJun 28, 13Jan 01, 15[H01L]
2015/0001,709 Semiconductor Device and Method of Stacking Semiconductor Die on a Fan-Out WLCSPApr 24, 14Jan 01, 15[H01L]
2015/0001,729 Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill MaterialJun 27, 13Jan 01, 15[H01L]
2015/0001,741 Semiconductor Device and Method of Forming an Interposer Including a Beveled EdgeJun 27, 13Jan 01, 15[H01L]
2015/0004,748 Methods of Forming Conductive Jumper TracesJun 27, 13Jan 01, 15[H01L]
2015/0004,750 Methods of Forming Conductive Materials on Contact PadsJun 27, 13Jan 01, 15[H01L]
2015/0004,756 Methods of Forming Conductive and Insulating LayersJun 27, 13Jan 01, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,936,969 Semiconductor device and method of singulating semiconductor wafer along modified region within non-active region formed by irradiating energy through mounting tapeMar 21, 12Jan 20, 15[H01L]
8,936,971 Integrated circuit packaging system with die paddles and method of manufacture thereofSep 16, 10Jan 20, 15[H01L]
8,937,371 Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSVJul 03, 13Jan 20, 15[H01L]
8,937,372 Integrated circuit package system with molded strip protrusionMar 21, 07Jan 20, 15[H01L]
8,937,379 Integrated circuit packaging system with trenched leadframe and method of manufacture thereofJul 03, 13Jan 20, 15[H01L]
8,937,393 Integrated circuit package system with device cavityMay 03, 07Jan 20, 15[H01L]
8,932,907 Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor dieDec 13, 12Jan 13, 15[H01L, H05K]
8,932,908 Semiconductor device and method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor dieMay 17, 13Jan 13, 15[H01L]
8,921,127 Semiconductor device and method of simultaneous testing of multiple interconnects for electro-migrationMar 21, 12Dec 30, 14[G01R, H01L]
8,921,161 Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around dieDec 31, 12Dec 30, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesMar 20, 12Sep 26, 13[H01L]
2013/0001,762 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieSep 10, 12Jan 03, 13[H01L]
2012/0273,937 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerApr 30, 11Nov 01, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFMar 23, 10May 12, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofJan 15, 10May 13, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPDec 17, 07Jun 18, 09[H01L]
2009/0140,408 INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH STACKING VIA INTERCONNECTNov 30, 07Jun 04, 09[H01L]
2009/0127,715 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTRUSIONNov 15, 07May 21, 09[H01L]

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