STATS CHIPPAC LTD.

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Technologies

Intl Class Technology # of Patents Rank
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 93232
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 2281
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 851
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 6109
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4121
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 4123
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 360
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 251
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 248
 
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 151

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0103,503 Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint ReliabilityDec 23, 13Apr 17, 14[H01L]
2014/0103,509 Semiconductor Device and Method of Forming Conductive Ink Layer as Interconnect Structure Between Semiconductor PackagesOct 16, 12Apr 17, 14[H01L]
2014/0103,527 Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect UnitsDec 19, 13Apr 17, 14[H01L]
2014/0097,475 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOFJan 16, 13Apr 10, 14[H01L]
2014/0091,454 Semiconductor Device and Method of Forming Supporting Layer Over Semiconductor Die in Thin Fan-Out Wafer Level Chip Scale PackageSep 28, 12Apr 03, 14[H01L]
2014/0091,455 Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor PackagingDec 05, 13Apr 03, 14[H01L]
2014/0091,482 Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSPMar 15, 13Apr 03, 14[H01L]
2014/0084,415 Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution LayerNov 27, 13Mar 27, 14[H01L]
2014/0084,424 Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating LayerNov 26, 13Mar 27, 14[H01L]
2014/0077,344 Semiconductor Device with Protective Layer Over Exposed Surfaces of Semiconductor DieNov 22, 13Mar 20, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,697,490 Flip chip interconnection structureJul 01, 11Apr 15, 14[H01L]
8,698,294 Integrated circuit package system including wide flange leadframeJan 24, 06Apr 15, 14[H01L]
8,698,297 Integrated circuit packaging system with stack deviceSep 23, 11Apr 15, 14[H01L]
8,699,232 Integrated circuit packaging system with interposer and method of manufacture thereofSep 20, 11Apr 15, 14[H05K]
8,692,365 Integrated circuit packaging system with thermal dispersal structures and method of manufacture thereofJun 17, 11Apr 08, 14[H01L]
8,692,377 Integrated circuit packaging system with plated leads and method of manufacture thereofMar 23, 11Apr 08, 14[H01L]
8,692,388 Integrated circuit package system with waferscale spacerJun 28, 12Apr 08, 14[H01L]
8,685,792 Integrated circuit package system with interposerFeb 29, 08Apr 01, 14[H01L]
8,685,797 Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereofAug 28, 12Apr 01, 14[H01L]
8,679,900 Integrated circuit packaging system with heat conduction and method of manufacture thereofDec 14, 11Mar 25, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFAug 24, 11Dec 15, 11[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofApr 03, 08Oct 08, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPDec 17, 07Jun 18, 09[H01L]
2009/0127,715 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTRUSIONNov 15, 07May 21, 09[H01L]
2008/0315,374 INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH MAGNETIC FILMJun 25, 07Dec 25, 08[H01L]
2008/0308,933 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT CONNECTION STRUCTURESJun 14, 07Dec 18, 08[H01L]
2008/0237,157 WAFER TRANSPORT SYSTEMMar 30, 07Oct 02, 08[H01L]
2008/0067,639 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCKSep 15, 06Mar 20, 08[H01L]
2008/0042,265 CHIP SCALE MODULE PACKAGE IN BGA SEMICONDUCTOR PACKAGEAug 15, 06Feb 21, 08[H01L]
2007/0235,878 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH POST-PASSIVATION INTERCONNECTION AND INTEGRATIONMar 30, 06Oct 11, 07[H01L]
2007/0170,558 STACKED INTEGRATED CIRCUIT PACKAGE SYSTEMJan 24, 06Jul 26, 07[H01L]
2007/0108,583 INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEMJul 17, 06May 17, 07[H01L]
2007/0108,635 INTEGRATED CIRCUIT PACKAGE SYSTEMMar 17, 06May 17, 07[H01L]
2007/0109,756 STACKED INTEGRATED CIRCUITS PACKAGE SYSTEMFeb 09, 06May 17, 07[H05K]
2007/0105,277 Solder joint flip chip interconnectionDec 14, 06May 10, 07[H01L]
2007/0093,000 PRE-MOLDED LEADFRAME AND METHOD THEREFOROct 21, 05Apr 26, 07[H01L]
2007/0085,184 STACKED DIE PACKAGING SYSTEMOct 13, 05Apr 19, 07[H01L]
2007/0001,296 BUMP FOR OVERHANG DEVICEAug 31, 06Jan 04, 07[H01L]

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Top Inventors for This Owner

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