STATS CHIPPAC LTD.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 149828
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3792
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1348
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 8110
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 671
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 6136
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4146
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 468
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 449
 
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 162

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0097,295 Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect VoidsDec 16, 14Apr 09, 15[H01L]
2015/0091,145 Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSPDec 11, 14Apr 02, 15[H01L]
2015/0091,157 Semiconductor Device and Method of Making an Embedded Wafer Level Ball Grid Array (EWLB) Package on Package (POP) Device With a Slotted Metal Carrier InterposerJun 14, 13Apr 02, 15[H01L]
2015/0091,165 Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-MigrationDec 08, 14Apr 02, 15[H01L]
2015/0084,172 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND METHOD OF MANUFACTURE THEREOFSep 26, 13Mar 26, 15[H01L]
2015/0084,178 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOFSep 25, 13Mar 26, 15[H01L]
2015/0084,206 Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor PackageSep 24, 13Mar 26, 15[H01L]
2015/0084,213 Semiconductor Device and Method of Controlling Warpage in Reconstituted WaferSep 25, 13Mar 26, 15[H01L]
2015/0061,123 Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL FormationOct 13, 14Mar 05, 15[H01L]
2015/0061,124 Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective LayerOct 24, 14Mar 05, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,006,031 Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumpsJun 23, 11Apr 14, 15[H01L]
9,006,882 Semiconductor device and method of forming recessed conductive vias in saw streetsMar 08, 10Apr 14, 15[H01L]
9,006,888 Semiconductor device and method of forming stress relief layer between die and interconnect structureSep 29, 11Apr 14, 15[H01L]
8,999,754 Integrated circuit package with molded cavityMay 03, 12Apr 07, 15[H01L]
8,999,760 Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structureJun 08, 12Apr 07, 15[H01L, H05K]
9,000,579 Integrated circuit package system with bonding in viaMar 30, 07Apr 07, 15[H01L]
8,993,376 Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor dieOct 28, 11Mar 31, 15[H01L]
8,993,377 Semiconductor device and method of bonding different size semiconductor die at the wafer levelSep 13, 11Mar 31, 15[H01L]
8,994,048 Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integrationDec 09, 10Mar 31, 15[H01L]
8,994,162 Semiconductor multi-package module including tape substrate land grid array package stacked over ball grid array packageJul 28, 09Mar 31, 15[H01L]
8,994,184 Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of FO-WLCSPMay 03, 13Mar 31, 15[H01L, H05K]
8,994,185 Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSPOct 01, 13Mar 31, 15[H01L, H05K]
8,994,192 Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereofDec 15, 11Mar 31, 15[H01L]
8,994,196 System and method for directional grinding on backside of a semiconductor waferJan 13, 11Mar 31, 15[B24B, H01L]
8,987,014 Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort testMay 15, 09Mar 24, 15[H01L]
8,987,056 Integrated circuit package system with support carrier and method of manufacture thereofNov 19, 08Mar 24, 15[H01L]
8,987,064 Integrated circuit packaging system with molded grid-array mechanism and method of manufacture thereofJan 11, 13Mar 24, 15[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
8,900,920 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerWithdrawnAug 11, 11Dec 02, 14[H01L, H05K]
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesABANMar 20, 12Sep 26, 13[H01L]
2013/0001,762 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieABANSep 10, 12Jan 03, 13[H01L]
2012/0273,937 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerABANApr 30, 11Nov 01, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFABANJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFABANJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFABANMar 23, 10May 12, 11[H01L]
2011/0024,890 Stackable Package By Using Internal Stacking ModulesABANSep 15, 10Feb 03, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateABANJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFABANJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFABANDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFABANNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSABANSep 26, 08Apr 01, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESABANMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingABANMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESABANJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierABANDec 26, 07Jul 02, 09[H01L]

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