STATS CHIPPAC LTD.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 147627
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3495
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1255
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 8112
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 672
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 5132
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4144
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 364
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 350
 
 
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 2170

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0361,423 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieAug 22, 14Dec 11, 14[H01L]
2014/0353,846 Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed EncapsulantAug 18, 14Dec 04, 14[H01L]
2014/0327,145 Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical InterconnectDec 14, 12Nov 06, 14[H01L]
2014/0300,002 Semiconductor Device and Method of Forming Conductive Vias Using Backside Via Reveal and Selective PassivationMar 21, 14Oct 09, 14[H01L]
2014/0295,618 Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression BondingMar 29, 13Oct 02, 14[H01L]
2014/0284,791 CORELESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOFMar 15, 14Sep 25, 14[H01L]
2014/0264,736 Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite SubstrateMay 28, 14Sep 18, 14[H01L]
2014/0264,786 Semiconductor Device Including RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction InterconnectJun 01, 14Sep 18, 14[H01L]
2014/0264,817 Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in PackageMar 13, 13Sep 18, 14[H01L]
2014/0264,850 Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump ConnectionsMay 12, 14Sep 18, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,906,740 Integrated circuit packaging system having dual sided connection and method of manufacture thereofApr 12, 11Dec 09, 14[H01L]
8,907,476 Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulationApr 13, 12Dec 09, 14[H01L]
8,907,498 Semiconductor device and method of forming a shielding layer between stacked semiconductor dieNov 30, 12Dec 09, 14[H01L]
8,900,920 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerAug 11, 11Dec 02, 14[H01L, H05K]
8,900,921 Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSVDec 11, 08Dec 02, 14[H01L]
8,900,929 Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formationMar 21, 12Dec 02, 14[H01L]
8,901,439 Integrated circuit package system with window openingAug 18, 06Dec 02, 14[H01R, G06K]
8,901,734 Semiconductor device and method of forming column interconnect structure to reduce wafer stressApr 03, 12Dec 02, 14[H01L]
8,901,755 Semiconductor device and method of forming conductive layer over metal substrate for electrical interconnect of semiconductor dieMar 20, 12Dec 02, 14[H01L]
8,895,358 Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSPSep 11, 09Nov 25, 14[H01L]
8,895,440 Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMVAug 06, 10Nov 25, 14[H01L]
8,896,109 Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor dieNov 21, 12Nov 25, 14[H01L]
8,896,115 Semiconductor device and method of forming shielding layer around back surface and sides of semiconductor wafer containing IPD structureApr 03, 12Nov 25, 14[H01L]
8,896,133 Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrateApr 25, 13Nov 25, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesMar 20, 12Sep 26, 13[H01L]
2013/0001,762 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieSep 10, 12Jan 03, 13[H01L]
2012/0273,937 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerApr 30, 11Nov 01, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFMar 23, 10May 12, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFJun 19, 09Dec 23, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofJan 15, 10May 13, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPDec 17, 07Jun 18, 09[H01L]
2009/0140,408 INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH STACKING VIA INTERCONNECTNov 30, 07Jun 04, 09[H01L]
2009/0127,715 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTRUSIONNov 15, 07May 21, 09[H01L]
2009/0001,549 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SYMMETRIC PACKAGINGJun 29, 07Jan 01, 09[H01L]

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