STATS CHIPPAC LTD.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 162725
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 5193
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 15130
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1353
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 9117
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 582
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4145
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 472
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 451
 
 
 
B08B CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL 252

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0013,148 Semiconductor Device and Method of Forming Wafer-Level Interconnect Structures with Advanced Dielectric CharacteristicsSep 22, 15Jan 14, 16[H01L]
2015/0380,310 Semiconductor Device and Method of Forming Conductive Vias by Direct Via Reveal with Organic PassivationJun 26, 14Dec 31, 15[H01L]
2015/0380,339 Semiconductor Device and Method of Forming Conductive Vias by Backside Via Reveal with CMPJun 26, 14Dec 31, 15[H01L]
2015/0364,394 Method for Building Up a Fan-Out RDL Structure with Fine Pitch Line-Width and Line-SpacingJun 16, 14Dec 17, 15[H01L]
2015/0364,430 Semiconductor Device and Method of Forming a Dampening Structure to Improve Board Level ReliabilityJun 16, 14Dec 17, 15[H01L]
2015/0357,274 Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMVAug 21, 15Dec 10, 15[H01L]
2015/0348,936 Semiconductor Device and Method of Forming Electromagnetic (EM) Shielding for LC CircuitsMay 26, 15Dec 03, 15[H01L]
2015/0325,553 Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POPJul 20, 15Nov 12, 15[H01L]
2015/0318,259 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH NO-REFLOW CONNECTION AND METHOD OF MANUFACTURE THEREOFApr 27, 15Nov 05, 15[H01L]
2015/0311,172 Semiconductor Device and Method of Forming Bump-on-Lead InterconnectionJun 19, 15Oct 29, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,252,032 Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive viasAug 03, 12Feb 02, 16[H01L]
9,252,066 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerAug 11, 11Feb 02, 16[H01L, H05K]
9,252,075 Semiconductor device and method of forming a conductive via-in-via structureSep 05, 12Feb 02, 16[H01L]
9,252,092 Semiconductor device and method of forming through mold hole with alignment and dimension controlJul 24, 13Feb 02, 16[H01L]
9,252,093 Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor waferNov 20, 13Feb 02, 16[H01L]
9,252,094 Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillarApr 30, 11Feb 02, 16[H01L]
9,252,130 Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bondingMar 29, 13Feb 02, 16[H01L]
9,252,172 Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity regionMay 31, 11Feb 02, 16[H01L]
9,245,770 Semiconductor device and method of simultaneous molding and thermalcompression bondingSep 26, 13Jan 26, 16[H01L]
9,245,772 Stackable package by using internal stacking modulesJul 10, 14Jan 26, 16[H01L]
9,245,834 Semiconductor device and method of forming compliant conductive interconnect structure in flipchip packageMar 16, 12Jan 26, 16[H01L]
9,240,331 Semiconductor device and method of making bumpless flipchip interconnect structuresSep 27, 13Jan 19, 16[H01L]
9,240,380 Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnectDec 14, 12Jan 19, 16[H01L, H05K]
9,240,384 Semiconductor device with solder bump formed on high topography plated Cu padsSep 17, 12Jan 19, 16[H01L]
9,236,278 Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereofSep 23, 11Jan 12, 16[H01L]
9,236,319 Stacked integrated circuit package systemMar 27, 08Jan 12, 16[H01L]
9,236,332 Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframeFeb 12, 13Jan 12, 16[H01L]
9,236,352 Semiconductor die and method of forming noise absorbing regions between THVs in peripheral region of the dieDec 22, 11Jan 12, 16[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
8,900,920 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerWithdrawnAug 11, 11Dec 02, 14[H01L, H05K]
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesABANMar 20, 12Sep 26, 13[H01L]
2013/0001,762 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieABANSep 10, 12Jan 03, 13[H01L]
2012/0273,937 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerABANApr 30, 11Nov 01, 12[H01L]
2012/0217,634 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierABANMar 02, 11Aug 30, 12[H01L]
2012/0211,881 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump ProcessABANApr 20, 10Aug 23, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFABANJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFABANJun 01, 10Dec 01, 11[H01L]
2011/0204,472 Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar FrameABANApr 30, 11Aug 25, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFABANMar 23, 10May 12, 11[H01L]
2011/0062,599 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANSep 17, 09Mar 17, 11[H01L]
2011/0024,890 Stackable Package By Using Internal Stacking ModulesABANSep 15, 10Feb 03, 11[H01L]
2011/0014,746 Semiconductor Device and Method of Forming Conductive TSV in Peripheral Region of Die Prior to Wafer SingulatonABANJul 17, 09Jan 20, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateABANJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFABANJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFABANDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFABANNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSABANSep 26, 08Apr 01, 10[H01L]

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