STATS ChipPAC, Ltd.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 152025
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3898
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1351
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 8109
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 6135
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 577
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4143
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 472
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 449
 
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 162

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0179,481 Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale PackagesDec 23, 13Jun 25, 15[H01L]
2015/0179,544 Semiconductor Device and Method of Wafer Thinning Involving Edge Trimming and CMPDec 19, 13Jun 25, 15[H01L]
2015/0179,555 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIALESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOFDec 20, 13Jun 25, 15[H01L]
2015/0179,570 Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out PackageDec 23, 13Jun 25, 15[H01L]
2015/0179,587 Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect StructureMar 03, 15Jun 25, 15[H01L]
2015/0179,602 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE INK AND METHOD OF MANUFACTURE THEREOFDec 20, 13Jun 25, 15[H01L]
2015/0179,616 Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary SubstrateFeb 17, 15Jun 25, 15[H01L]
2015/0171,002 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED COMPONENT AND METHOD OF MANUFACTURE THEREOFDec 01, 14Jun 18, 15[H01L]
2015/0171,024 Semiconductor Device and Method of Reducing Warpage Using a Silicon to Encapsulant RatioDec 17, 13Jun 18, 15[H01L]
2015/0155,248 Semiconductor Device and Method of Forming Repassivation Layer for Robust Low Cost Fan-Out Semiconductor PackageFeb 09, 15Jun 04, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,087,701 Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POPApr 30, 11Jul 21, 15[H01L]
9,087,930 Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress reliefMay 09, 14Jul 21, 15[H01L]
9,082,638 Semiconductor device with cross-talk isolation using M-capAug 10, 12Jul 14, 15[H01L]
9,082,780 Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layerMar 23, 12Jul 14, 15[H01L]
9,082,806 Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSPJul 26, 11Jul 14, 15[H01L]
9,082,832 Semiconductor device and method of forming protection and support structure for conductive interconnect structureMay 22, 12Jul 14, 15[H01L]
9,082,887 Integrated circuit packaging system with posts and method of manufacture thereofAug 13, 13Jul 14, 15[H01L]
9,084,377 Integrated circuit package system with mounting features for clearanceMar 30, 07Jul 14, 15[H05K]
9,076,655 Semiconductor device and method of forming through-silicon-via with sacrificial layerJan 16, 13Jul 07, 15[H01L]
9,076,724 Integrated circuit system with debonding adhesive and method of manufacture thereofSep 26, 13Jul 07, 15[H01L]
9,076,737 Integrated circuit packaging system with bumps and method of manufacture thereofJun 19, 09Jul 07, 15[H01L]
9,076,802 Dual-sided film-assist molding processSep 25, 13Jul 07, 15[H01L]
9,076,803 Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structureOct 25, 13Jul 07, 15[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
8,900,920 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerWithdrawnAug 11, 11Dec 02, 14[H01L, H05K]
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesABANMar 20, 12Sep 26, 13[H01L]
2013/0001,762 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieABANSep 10, 12Jan 03, 13[H01L]
2012/0273,937 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerABANApr 30, 11Nov 01, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFABANJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFABANJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFABANMar 23, 10May 12, 11[H01L]
2011/0024,890 Stackable Package By Using Internal Stacking ModulesABANSep 15, 10Feb 03, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateABANJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFABANJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFABANDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFABANNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSABANSep 26, 08Apr 01, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESABANMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingABANMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESABANJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierABANDec 26, 07Jul 02, 09[H01L]

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