STATS CHIPPAC LTD.

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Technologies

Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 146227
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3095
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1251
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 7112
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 671
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 5137
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4146
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 367
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 350
 
 
 
B29C SHAPING OR JOINING OF PLASTICS; SHAPING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL; AFTER- TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING 291

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0252,573 Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLBFeb 28, 14Sep 11, 14[H01L]
2014/0252,631 Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor DieJun 04, 10Sep 11, 14[H01L]
2014/0252,641 Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die PackageFeb 21, 14Sep 11, 14[H01L]
2014/0252,654 Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor DieMay 22, 14Sep 11, 14[H01L]
2014/0246,779 Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die For Stress ReliefMay 09, 14Sep 04, 14[H01L]
2014/0239,495 Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSPMay 01, 14Aug 28, 14[H01L]
2014/0239,496 Semiconductor Device and Method of Forming Micro-Vias Partially Through Insulating Material Over Bump Interconnect Conductive Layer for Stress ReliefMay 02, 14Aug 28, 14[H01L]
2014/0239,509 Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSVMay 01, 14Aug 28, 14[H01L]
2014/0231,989 Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During EncapsulationApr 30, 14Aug 21, 14[H01L]
2014/0225,256 Semiconductor Device with Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and SubstrateApr 18, 14Aug 14, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,835,301 Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor waferFeb 28, 11Sep 16, 14[H01L]
8,836,097 Semiconductor device and method of forming pre-molded substrate to reduce warpage during die moldingFeb 16, 13Sep 16, 14[H01L]
8,836,114 Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layersNov 16, 12Sep 16, 14[H01L, H05K]
8,822,281 Semiconductor device and method of forming TMV and TSV in WLCSP using same carrierFeb 23, 10Sep 02, 14[H01L]
8,823,160 Integrated circuit package system having cavityAug 22, 08Sep 02, 14[H01L]
8,823,182 Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulantJul 05, 13Sep 02, 14[H01L]
8,823,466 Miniaturized wide-band baluns for RF applicationsOct 27, 09Sep 02, 14[H03H, H01F]
8,815,643 Method of fabricating semiconductor die with through-hole via on saw streets and through-hole via in active area of dieFeb 07, 11Aug 26, 14[H01L]
8,815,650 Integrated circuit packaging system with formed under-fill and method of manufacture thereofSep 23, 11Aug 26, 14[H01L]
8,816,404 Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulantSep 16, 11Aug 26, 14[H01L]
8,816,487 Integrated circuit packaging system with package-in-package and method of manufacture thereofMar 13, 09Aug 26, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFMar 23, 10May 12, 11[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFJun 19, 09Dec 23, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFNov 20, 08May 20, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPDec 17, 07Jun 18, 09[H01L]
2009/0127,715 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTRUSIONNov 15, 07May 21, 09[H01L]
2009/0001,549 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SYMMETRIC PACKAGINGJun 29, 07Jan 01, 09[H01L]
2008/0315,374 INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH MAGNETIC FILMJun 25, 07Dec 25, 08[H01L]
2008/0308,933 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT CONNECTION STRUCTURESJun 14, 07Dec 18, 08[H01L]
2008/0251,901 STACKED INTEGRATED CIRCUIT PACKAGE SYSTEMApr 28, 08Oct 16, 08[H01L]
2008/0237,157 WAFER TRANSPORT SYSTEMMar 30, 07Oct 02, 08[H01L]
2008/0185,737 INTEGRATED CIRCUIT SYSTEM WITH PRE-CONFIGURED BOND WIRE BALLFeb 01, 08Aug 07, 08[B23K, H01L]
2008/0067,639 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCKSep 15, 06Mar 20, 08[H01L]

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Top Inventors for This Owner

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