STATS CHIPPAC LTD.

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Intl Class Technology # of Patents/ App Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 144826
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 2998
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1250
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 7115
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 672
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 5135
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4147
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 366
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 350
 
 
 
B29C SHAPING OR JOINING OF PLASTICS; SHAPING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL; AFTER- TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING 290

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2014/0225,256 Semiconductor Device with Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and SubstrateApr 18, 14Aug 14, 14[H01L]
2014/0225,257 Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask PatchApr 22, 14Aug 14, 14[H01L]
2014/0225,279 Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress ReliefApr 21, 14Aug 14, 14[H01L]
2014/0217,597 Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP PackageFeb 05, 13Aug 07, 14[H01L]
2014/0217,609 Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw StreetApr 09, 14Aug 07, 14[H01L]
2014/0203,443 Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer CoreMar 25, 14Jul 24, 14[H01L]
2014/0197,540 Extended Redistribution Layers Bumped WaferMar 14, 14Jul 17, 14[H01L]
2014/0197,548 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANISM AND METHOD OF MANUFACTURE THEREOFJan 11, 13Jul 17, 14[H01L]
2014/0199,838 Semiconductor Device and Method of Forming Through-Silicon-Via with Sacrificial LayerJan 16, 13Jul 17, 14[H01L]
2014/0183,718 Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale PackagesSep 25, 13Jul 03, 14[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,809,119 Integrated circuit packaging system with plated leads and method of manufacture thereofMay 17, 13Aug 19, 14[H01L]
8,809,191 Semiconductor device and method of forming UBM structure on back surface of TSV semiconductor waferDec 13, 11Aug 19, 14[H01L]
8,810,011 Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposerAug 09, 12Aug 19, 14[H01L]
8,810,015 Integrated circuit packaging system with high lead count and method of manufacture thereofJun 14, 09Aug 19, 14[H01L]
8,810,017 Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereofJun 28, 12Aug 19, 14[H01L]
8,810,018 Stacked integrated circuit package system with face to face stack configurationFeb 03, 06Aug 19, 14[H01L]
8,810,019 Integrated circuit package system with stacked dieFeb 06, 12Aug 19, 14[H01L]
8,810,024 Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect unitsMar 23, 12Aug 19, 14[H01L]
8,810,029 Solder joint flip chip interconnectionFeb 06, 12Aug 19, 14[H01L]
8,802,500 Integrated circuit packaging system with leads and method of manufacture thereofNov 11, 10Aug 12, 14[H01L]
8,802,501 Integrated circuit packaging system with island terminals and method of manufacture thereofJul 21, 11Aug 12, 14[H01L]
8,802,505 Semiconductor device and method of forming a protective layer on a backside of the waferSep 30, 08Aug 12, 14[H01L]
8,802,555 Integrated circuit packaging system with interconnects and method of manufacture thereofMar 23, 11Aug 12, 14[H01L]
8,803,299 Stacked integrated circuit package systemFeb 27, 06Aug 12, 14[H01L]
8,803,300 Integrated circuit packaging system with protective coating and method of manufacture thereofSep 24, 10Aug 12, 14[H01L]
8,803,330 Integrated circuit package system with mounting structureSep 27, 08Aug 12, 14[H01L]
8,803,630 Miniaturized wide-band baluns for RF applicationsOct 14, 09Aug 12, 14[H03H, H01F, H01P]
8,796,137 Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnectJun 24, 10Aug 05, 14[H01L]
8,796,846 Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSPOct 02, 09Aug 05, 14[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFMar 23, 10May 12, 11[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFJun 19, 09Dec 23, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFNov 20, 08May 20, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPDec 17, 07Jun 18, 09[H01L]
2009/0127,715 MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTRUSIONNov 15, 07May 21, 09[H01L]
2009/0001,549 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SYMMETRIC PACKAGINGJun 29, 07Jan 01, 09[H01L]
2008/0315,374 INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH MAGNETIC FILMJun 25, 07Dec 25, 08[H01L]
2008/0308,933 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT CONNECTION STRUCTURESJun 14, 07Dec 18, 08[H01L]
2008/0251,901 STACKED INTEGRATED CIRCUIT PACKAGE SYSTEMApr 28, 08Oct 16, 08[H01L]
2008/0237,157 WAFER TRANSPORT SYSTEMMar 30, 07Oct 02, 08[H01L]
2008/0185,737 INTEGRATED CIRCUIT SYSTEM WITH PRE-CONFIGURED BOND WIRE BALLFeb 01, 08Aug 07, 08[B23K, H01L]
2008/0067,639 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCKSep 15, 06Mar 20, 08[H01L]

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