STATS CHIPPAC LTD.

Patent Owner

Follow Compare Add to Portfolio 5Status Updates

Stats

Details

Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 177180
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 7135
 
 
 
B81C PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS 225
 
 
 
B81B MICRO-STRUCTURAL DEVICES OR SYSTEMS, e.g. MICRO-MECHANICAL DEVICES 128
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 1129

Top Patents (by citation)

Upgrade to the Premium Level to View Top Patents for this Owner. Learn More

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0197,022 Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor DieMar 11, 16Jul 07, 16[H01L]
2016/0197,059 Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive ChannelsMar 14, 16Jul 07, 16[H01L]
2016/0190,054 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER SUPPORT STRUCTURE MECHANISM AND METHOD OF MANUFACTURE THEREOFJul 06, 15Jun 30, 16[H01L]
2016/0190,056 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANISM AND METHOD OF MANUFACTURE THEREOFDec 28, 15Jun 30, 16[H01L]
2016/0163,675 Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer FormFeb 01, 16Jun 09, 16[H01L]
2016/0148,882 Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground ShieldJan 29, 16May 26, 16[H01L]
2016/0141,238 Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLB-MLP)Jan 27, 16May 19, 16[H01L]
2016/0118,332 Semiconductor Device and Method of Fabricating 3D Package With Short Cycle Time and High YieldOct 20, 15Apr 28, 16[H01L]
2016/0118,333 Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High YieldDec 16, 15Apr 28, 16[H01L]
2016/0111,410 Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical InterconnectDec 16, 15Apr 21, 16[H01L]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,385,066 Integrated circuit packaging system with molded laser via interposer and method of manufacture thereofMay 20, 14Jul 05, 16[H01L]
9,385,100 Integrated circuit packaging system with surface treatment and method of manufacture thereofMar 17, 15Jul 05, 16[H01L]
9,385,101 Semiconductor device and method of forming bump-on-lead interconnectionJun 19, 15Jul 05, 16[H01L]
9,379,064 Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the dieApr 28, 15Jun 28, 16[H01L]
9,379,084 Semiconductor device and method of self-confinement of conductive bump material during reflow without solder maskApr 09, 15Jun 28, 16[H01L]
9,362,161 Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor packageMar 20, 14Jun 07, 16[H01L]
9,355,939 Integrated circuit package stacking system with shielding and method of manufacture thereofMar 02, 10May 31, 16[H01L]
9,355,962 Integrated circuit package stacking system with redistribution and method of manufacture thereofJun 12, 09May 31, 16[H01L]
9,355,983 Integrated circuit packaging system with interposer structure and method of manufacture thereofJun 27, 14May 31, 16[H01L]
9,355,993 Integrated circuit system with debonding adhesive and method of manufacture thereofJul 03, 15May 31, 16[H01L]

View all patents..

Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
8,900,920 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerWithdrawnAug 11, 11Dec 02, 14[H01L, H05K]
2012/0211,881 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump ProcessABANApr 20, 10Aug 23, 12[H01L]
2012/0119,345 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOFABANNov 15, 10May 17, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFABANJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFABANJun 01, 10Dec 01, 11[H01L]
2011/0248,391 INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOFABANMay 18, 10Oct 13, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFABANMar 23, 10May 12, 11[H01L]
2011/0062,599 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANSep 17, 09Mar 17, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateABANJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFABANJun 19, 09Dec 23, 10[H01L]
2010/0237,481 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOFABANMar 20, 09Sep 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFABANDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFABANNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSABANSep 26, 08Apr 01, 10[H01L]
2009/0283,889 INTEGRATED CIRCUIT PACKAGE SYSTEMABANMay 16, 08Nov 19, 09[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESABANMar 26, 08Oct 01, 09[H01L]
2009/0243,069 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTIONABANMar 26, 08Oct 01, 09[H01L]

View all patents..

Top Inventors for This Owner

Upgrade to the Premium Level to View Top Inventors for this Owner. Learn More

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to -1 comparisons!

We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.