STATS CHIPPAC LTD.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 166193
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 6140
 
 
 
B81C PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICRO-STRUCTURAL DEVICES OR SYSTEMS 323
 
 
 
B81B MICRO-STRUCTURAL DEVICES OR SYSTEMS, e.g. MICRO-MECHANICAL DEVICES 227
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 1121

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2016/0233,168 Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor PackageApr 15, 16Aug 11, 16[H01L]
2016/0214,857 Semiconductor Device and Method of Forming MEMS PackageJan 27, 16Jul 28, 16[B81C, B81B]
2016/0218,089 Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded Within Interconnect StructureApr 01, 16Jul 28, 16[H01L]
2016/0197,022 Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor DieMar 11, 16Jul 07, 16[H01L]
2016/0197,059 Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive ChannelsMar 14, 16Jul 07, 16[H01L]
2016/0190,054 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER SUPPORT STRUCTURE MECHANISM AND METHOD OF MANUFACTURE THEREOFJul 06, 15Jun 30, 16[H01L]
2016/0190,056 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANISM AND METHOD OF MANUFACTURE THEREOFDec 28, 15Jun 30, 16[H01L]
2016/0163,675 Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer FormFeb 01, 16Jun 09, 16[H01L]
2016/0148,882 Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground ShieldJan 29, 16May 26, 16[H01L]
2016/0141,238 Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLB-MLP)Jan 27, 16May 19, 16[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9,418,962 Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposersMay 12, 15Aug 16, 16[H01L]
9,412,624 Integrated circuit packaging system with substrate and method of manufacture thereofJun 26, 14Aug 09, 16[H01L]
9,406,531 Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereofMar 28, 14Aug 02, 16[H01L]
9,406,642 Integrated circuit packaging system with insulated trace and method of manufacture thereofMar 09, 15Aug 02, 16[H01L]
9,401,347 Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSVJan 20, 15Jul 26, 16[H01L]
9,385,066 Integrated circuit packaging system with molded laser via interposer and method of manufacture thereofMay 20, 14Jul 05, 16[H01L]
9,385,100 Integrated circuit packaging system with surface treatment and method of manufacture thereofMar 17, 15Jul 05, 16[H01L]
9,385,101 Semiconductor device and method of forming bump-on-lead interconnectionJun 19, 15Jul 05, 16[H01L]
9,379,064 Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the dieApr 28, 15Jun 28, 16[H01L]
9,379,084 Semiconductor device and method of self-confinement of conductive bump material during reflow without solder maskApr 09, 15Jun 28, 16[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
8,900,920 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layerWithdrawnAug 11, 11Dec 02, 14[H01L, H05K]
2012/0326,324 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANJun 22, 11Dec 27, 12[H01L]
2012/0211,881 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump ProcessABANApr 20, 10Aug 23, 12[H01L]
2012/0119,345 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOFABANNov 15, 10May 17, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFABANJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFABANJun 01, 10Dec 01, 11[H01L]
2011/0248,391 INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM WITH LEAD OVERLAP AND METHOD OF MANUFACTURE THEREOFABANMay 18, 10Oct 13, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFABANMar 23, 10May 12, 11[H01L]
2011/0062,599 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANSep 17, 09Mar 17, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateABANJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFABANJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFABANDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFABANNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSABANSep 26, 08Apr 01, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESABANMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingABANMar 12, 08Sep 17, 09[H01L]
2009/0212,441 Semiconductor Interconnect Structure with Stacked Vias Separated by Signal Line and Method ThereforABANFeb 22, 08Aug 27, 09[H01L]

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Top Inventors for This Owner

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