STATS CHIPPAC LTD.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 149127
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 3597
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1254
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 8117
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 671
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 6136
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4146
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 369
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 347
 
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 162

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0054,151 Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect StructureOct 01, 14Feb 26, 15[H01L]
2015/0054,167 Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor DieSep 30, 14Feb 26, 15[H01L]
2015/0041,985 Semiconductor Device and Method of Making Wafer Level Chip Scale PackageAug 01, 14Feb 12, 15[H01L]
2015/0028,471 Semiconductor Device and Method of Forming Through Mold Hole with Alignment and Dimension ControlJul 24, 13Jan 29, 15[H01L]
2015/0028,496 Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect StructureOct 14, 14Jan 29, 15[H01L]
2015/0021,754 Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal ManagementOct 08, 14Jan 22, 15[H01L]
2015/0008,597 Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During SingulationSep 23, 14Jan 08, 15[H01L]
2015/0001,703 Semiconductor Device and Method of Individual Die Bonding Followed by Simultaneous Multiple Die Thermal Compression BondingJun 27, 13Jan 01, 15[H01L]
2015/0001,705 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED PAD ON LAYERED SUBSTRATE AND METHOD OF MANUFACTURE THEREOFJun 27, 13Jan 01, 15[H01L]
2015/0001,707 Semiconductor Device and Method of Using Substrate With Conductive Posts and Protective Layers to Form Embedded Sensor Die PackageJun 28, 13Jan 01, 15[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,962,393 Integrated circuit packaging system with heat shield and method of manufacture thereofSep 23, 11Feb 24, 15[H01L]
8,962,476 Method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axisMay 14, 13Feb 24, 15[H01L]
8,963,309 Semiconductor package with penetrable encapsulant joining semiconductor die and method thereofJul 13, 11Feb 24, 15[H01L]
8,963,320 Integrated circuit packaging system with thermal structures and method of manufacture thereofJun 20, 12Feb 24, 15[H01L]
8,963,326 Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migrationDec 06, 11Feb 24, 15[H01L]
8,956,914 Integrated circuit package system with overhang dieJun 26, 07Feb 17, 15[H01L]
8,957,509 Integrated circuit packaging system with thermal emission and method of manufacture thereofJun 23, 11Feb 17, 15[H01L]
8,957,515 Integrated circuit package system with array of external interconnectsNov 07, 07Feb 17, 15[H01L]
8,957,530 Integrated circuit packaging system with embedded circuitry and postFeb 08, 11Feb 17, 15[H01L]
8,951,834 Methods of forming solder balls in semiconductor packagesJun 28, 13Feb 10, 15[G01R, H01L]
8,951,839 Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSPMar 15, 10Feb 10, 15[H01L, H05K]
8,951,904 Integrated circuit package system with post-passivation interconnection and integrationApr 25, 12Feb 10, 15[H01L]
8,952,529 Semiconductor device with conductive layer over substrate with vents to channel bump material and reduce interconnect voidsNov 22, 11Feb 10, 15[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Filing Date Issue/Pub Date Intl Class
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesMar 20, 12Sep 26, 13[H01L]
2013/0001,762 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieSep 10, 12Jan 03, 13[H01L]
2012/0273,937 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerApr 30, 11Nov 01, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFMar 23, 10May 12, 11[H01L]
2011/0024,890 Stackable Package By Using Internal Stacking ModulesSep 15, 10Feb 03, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSSep 26, 08Apr 01, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPDec 17, 07Jun 18, 09[H01L]

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Top Inventors for This Owner

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