STATS CHIPPAC LTD.

Patent Owner

Compare Create Portfolio
11Status Updates

Stats

Details

Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 148827
 
 
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 35100
 
 
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1351
 
 
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 8107
 
 
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 672
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 6143
 
 
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4140
 
 
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 467
 
 
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 445
 
 
 
B24B MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING 160

Top Patents (by citation)

Upgrade to the Premium Level to View Top Patents for this Owner. Learn More

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2015/0061,123 Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL FormationOct 13, 14Mar 05, 15[H01L]
2015/0061,124 Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective LayerOct 24, 14Mar 05, 15[H01L]
2015/0054,151 Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect StructureOct 01, 14Feb 26, 15[H01L]
2015/0054,167 Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor DieSep 30, 14Feb 26, 15[H01L]
2015/0041,985 Semiconductor Device and Method of Making Wafer Level Chip Scale PackageAug 01, 14Feb 12, 15[H01L]
2015/0028,471 Semiconductor Device and Method of Forming Through Mold Hole with Alignment and Dimension ControlJul 24, 13Jan 29, 15[H01L]
2015/0028,496 Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect StructureOct 14, 14Jan 29, 15[H01L]
2015/0021,754 Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal ManagementOct 08, 14Jan 22, 15[H01L]
2015/0008,597 Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During SingulationSep 23, 14Jan 08, 15[H01L]
2015/0001,703 Semiconductor Device and Method of Individual Die Bonding Followed by Simultaneous Multiple Die Thermal Compression BondingJun 27, 13Jan 01, 15[H01L]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,980,691 Semiconductor device and method of forming low profile 3D fan-out packageJun 28, 13Mar 17, 15[H01L]
8,981,548 Integrated circuit package system with reliefMay 20, 08Mar 17, 15[H01L]
8,981,577 Integrated circuit packaging system with interconnect and method of manufacture thereofMar 24, 10Mar 17, 15[H01L]
8,981,866 Semiconductor device and method of forming RF balun having reduced capacitive coupling and high CMRRAug 09, 12Mar 17, 15[H03H, H01L, H01P]
8,975,111 Wafer level die integration and method thereforJun 27, 11Mar 10, 15[H01L]
8,975,665 Integrated circuit packaging system with coreless substrate and method of manufacture thereofJan 16, 13Mar 10, 15[H01L]
8,975,980 Semiconductor device having balanced band-pass filter implemented with LC resonatorsSep 04, 13Mar 10, 15[H03H, H01F, H01L, H01P]
8,969,136 Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereofMar 25, 11Mar 03, 15[H01L]
8,970,044 Integrated circuit packaging system with vertical interconnects and method of manufacture thereofJun 23, 11Mar 03, 15[H01L]
8,962,393 Integrated circuit packaging system with heat shield and method of manufacture thereofSep 23, 11Feb 24, 15[H01L]

View all patents..

Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesABANMar 20, 12Sep 26, 13[H01L]
2013/0001,762 Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor DieABANSep 10, 12Jan 03, 13[H01L]
2012/0273,937 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerABANApr 30, 11Nov 01, 12[H01L]
2011/0316,163 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOFABANJun 24, 10Dec 29, 11[H01L]
2011/0306,168 INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOFABANAug 24, 11Dec 15, 11[H01L]
2011/0291,264 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOFABANJun 01, 10Dec 01, 11[H01L]
2011/0108,966 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOFABANMar 23, 10May 12, 11[H01L]
2011/0024,890 Stackable Package By Using Internal Stacking ModulesABANSep 15, 10Feb 03, 11[H01L]
2010/0327,406 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In SubstrateABANJun 26, 09Dec 30, 10[H01L]
2010/0320,591 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACT PADS AND METHOD OF MANUFACTURE THEREOFABANJun 19, 09Dec 23, 10[H01L]
2010/0133,534 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND FLIP CHIP AND METHOD OF MANUFACTURE THEREOFABANDec 03, 08Jun 03, 10[H01L]
2010/0123,230 INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING BUMPED LEAD AND METHOD OF MANUFACTURE THEREOFABANNov 20, 08May 20, 10[H01L]
2010/0117,230 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANJan 15, 10May 13, 10[H01L]
2010/0078,831 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESSABANSep 26, 08Apr 01, 10[H01L]
2009/0250,814 Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method ThereofABANApr 03, 08Oct 08, 09[H01L]
2009/0243,068 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURESABANMar 26, 08Oct 01, 09[H01L]
2009/0233,436 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingABANMar 12, 08Sep 17, 09[H01L]
2009/0191,029 SYSTEM FOR HANDLING SEMICONDUCTOR DIESABANJan 30, 08Jul 30, 09[H01L]
2009/0170,241 Semiconductor Device and Method of Forming the Device Using Sacrificial CarrierABANDec 26, 07Jul 02, 09[H01L]
2009/0152,740 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIPABANDec 17, 07Jun 18, 09[H01L]

View all patents..

Top Inventors for This Owner

Upgrade to the Premium Level to View Top Inventors for this Owner. Learn More

We are sorry but your current selection exceeds the maximum number of comparisons () for this membership level. Upgrade to our Level for up to -1 comparisons!

We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.