STATS CHIPPAC PTE. LTE.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 172125
 
  
 
H05K PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS 6790
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 15144
 
  
 
H03H IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS 1556
 
  
 
H01R ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS 8125
 
  
 
B23K SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM 687
 
  
 
H01P WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE 555
 
  
 
B32B LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM4153
 
  
 
H01F MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES 480
 
  
 
B81B MICRO-STRUCTURAL DEVICES OR SYSTEMS, e.g. MICRO-MECHANICAL DEVICES 330

Top Patents (by citation)

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Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2018/0019,195 Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System In PackageSep 15, 17Jan 18, 18[H01L]
2017/0294,406 Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale PackagesJun 19, 17Oct 12, 17[H01L]
2017/0271,305 Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale PackagesJun 06, 17Sep 21, 17[H01L]
2017/0260,043 Semiconductor Device and Method of Forming MEMS PackageJun 01, 17Sep 14, 17[B81B]
2017/0263,470 Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLBMay 25, 17Sep 14, 17[H01L]
2017/0186,690 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench in SubstrateMar 16, 17Jun 29, 17[H01L]
2017/0069,565 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SINGLE-LAYER SUPPORT STRUCTURESep 06, 16Mar 09, 17[H01L]
2017/0062,390 Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed EncapsulantNov 11, 16Mar 02, 17[H01L]
2017/0018,507 Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor DieSep 29, 16Jan 19, 17[H01L]
2016/0329,310 Methods of Forming Conductive and Insulating LayersJul 05, 16Nov 10, 16[H01L]

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9922915 Bump-on-lead flip chip interconnectionAug 13, 13Mar 20, 18[H01L]
9922955 Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSPMar 04, 10Mar 20, 18[H01L]
9905491 Interposer substrate designs for semiconductor packagesSep 27, 13Feb 27, 18[H01L]
9899286 Semiconductor device and method of self-confinement of conductive bump material during reflow without solder maskMay 12, 16Feb 20, 18[H01L]
9893017 Double-sided semiconductor package and dual-mold method of making sameApr 01, 16Feb 13, 18[H01L]
9893045 Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnectDec 16, 15Feb 13, 18[H01L, H05K]
9881894 Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integrationFeb 20, 13Jan 30, 18[H01L]
9875911 Semiconductor device and method of forming interposer with opening to contain semiconductor dieFeb 26, 10Jan 23, 18[H01L]
9875973 Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layersApr 30, 13Jan 23, 18[H01L]
9865482 Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete componentApr 03, 12Jan 09, 18[H01L]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2016/0190,056 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE MECHANISM AND METHOD OF MANUFACTURE THEREOFAbandonedDec 28, 15Jun 30, 16[H01L]
2015/0179,555 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIALESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOFAbandonedDec 20, 13Jun 25, 15[H01L]
2015/0179,602 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE INK AND METHOD OF MANUFACTURE THEREOFAbandonedDec 20, 13Jun 25, 15[H01L]
2015/0001,741 Semiconductor Device and Method of Forming an Interposer Including a Beveled EdgeAbandonedJun 27, 13Jan 01, 15[H01L]
2015/0004,750 Methods of Forming Conductive Materials on Contact PadsAbandonedJun 27, 13Jan 01, 15[H01L]
2014/0335,655 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTUREAbandonedJul 25, 14Nov 13, 14[H01L]
2014/0312,512 Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerAbandonedJul 01, 14Oct 23, 14[H01L]
2014/0165,389 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD FRAMEAbandonedDec 14, 12Jun 19, 14[H01L]
2014/0159,236 Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP CoatingAbandonedFeb 14, 14Jun 12, 14[H01L]
2014/0070,427 Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL BondingAbandonedNov 17, 13Mar 13, 14[H01L]
2014/0008,783 Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder TapeAbandonedSep 09, 13Jan 09, 14[H01L]
2013/0328,220 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSIST AND METHOD OF MANUFACTURE THEREOFAbandonedJun 12, 12Dec 12, 13[H01L]
2013/0256,840 Semiconductor Device and Method of Forming Protective Coating Material Over Semiconductor Wafer to Reduce Lamination Tape ResidueAbandonedMay 31, 13Oct 03, 13[H01L]
2013/0256,923 Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and PressureAbandonedMay 30, 13Oct 03, 13[H01L]
2013/0249,073 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOFAbandonedMar 22, 12Sep 26, 13[H01L]
2013/0249,076 Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent TracesAbandonedMar 20, 12Sep 26, 13[H01L]
2013/0249,101 Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect UnitsAbandonedMay 22, 12Sep 26, 13[H01L]
2013/0113,118 Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning LayerAbandonedNov 04, 11May 09, 13[H01L]
2013/0075,923 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOFAbandonedSep 23, 11Mar 28, 13[H01L]
2013/0049,188 Semiconductor Device and Method of Forming TIM Within Recesses of MUF MaterialAbandonedAug 25, 11Feb 28, 13[H01L]

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Top Inventors for This Owner

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