SYNOPSYS, INC.

Patent Owner

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Details

Technologies

Intl Class Technology # of Patents Rank
 
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 93442
 
 
 
G11C STATIC STORES 13648
 
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 104158
 
 
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 7736
 
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 7260
 
 
 
G06K RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS 23118
 
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 2373
 
 
 
H03K PULSE TECHNIQUE 2284
 
 
 
G02B OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS 16144
 
 
 
H04B TRANSMISSION 13151

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
5,858,580 Phase shifting circuit manufacture method and apparatusSep 17, 97Jan 12, 99[G03F]239
6,470,489 Design rule checking system and methodSep 16, 98Oct 22, 02[G03F, G06F]228
6,370,679 Data hierarchy layout correction and verification method and apparatusSep 16, 98Apr 09, 02[G06F]220
6,009,251 Method and system for layout verification of an integrated circuit design with reusable subdesignsSep 30, 97Dec 28, 99[G06F]212
5,684,951 Method and system for user authorization over a multi-user computer systemMar 20, 96Nov 04, 97[G06F]181
6,557,145 Method for design optimization using logical and physical informationMar 06, 01Apr 29, 03[G06F]143
6,324,675 Efficient iterative, gridless, cost-based fine router for computer controlled integrated circuit designDec 18, 98Nov 27, 01[G04F]143
6,453,457 Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layoutSep 29, 00Sep 17, 02[G03F, G06F]141
7,155,689 Design-manufacturing interface via a unified modelOct 07, 03Dec 26, 06[G06F]137
6,286,128 Method for design optimization using logical and physical informationJun 12, 98Sep 04, 01[G06F]134

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0089,137 RATE DISTORTION OPTIMIZATION IN IMAGE AND VIDEO ENCODINGApr 16, 12Apr 11, 13[H04N]
2013/0089,150 VISUAL QUALITY MEASURE FOR REAL-TIME VIDEO PROCESSINGApr 19, 12Apr 11, 13[H04N]
2013/0091,480 PARASITIC EXTRACTION FOR SEMICONDUCTORSOct 05, 12Apr 11, 13[G06F]
2013/0085,738 EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTIONNov 26, 12Apr 04, 13[G06F]
2013/0086,535 INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATANov 26, 12Apr 04, 13[G06F]
2013/0080,847 MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIESSep 23, 11Mar 28, 13[G11C, G06F]
2013/0074,024 LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECKNov 13, 12Mar 21, 13[G06F]
2013/0065,380 METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATUREJan 13, 12Mar 14, 13[H01L]
2013/0067,437 Providing SystemVerilog Testing Harness for a Standardized Testing LanguageSep 13, 12Mar 14, 13[G06F]
2013/0047,127 METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREESAug 17, 11Feb 21, 13[G06F]

View all Publication..

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,438,530 Connection navigation in electronic design automationOct 30, 09May 07, 13[G06F]
8,433,879 RFID tag semiconductor chip with memory management unit (MMU) to make only one time programmable (OTP) memory appear multiple times programmable (MTP)Dec 31, 07Apr 30, 13[G06F]
8,434,035 Relative positioning of circuit elements in circuit designJul 05, 12Apr 30, 13[G06F]
8,434,040 Clock-reconvergence pessimism removal in hierarchical static timing analysisApr 27, 11Apr 30, 13[G06F]
8,434,047 Multi-level clock gating circuitry transformationJan 25, 11Apr 30, 13[G06F]
8,429,375 Memory management unit (MMU) to make only one time programmable (OTP) memory appear multiple times programmable (MTP)Jun 15, 07Apr 23, 13[G06F]
8,429,473 Increasing PRPG-based compression by delayed justificationDec 15, 10Apr 23, 13[G06F]
8,429,583 Circuit design and retimingApr 29, 09Apr 23, 13[G06F]
8,429,589 Generating net routing constraints for place and routeSep 03, 10Apr 23, 13[G06F]
8,423,917 Modeling thin-film stack topography effect on a photolithography processJul 30, 09Apr 16, 13[G06F]

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Top Inventors for This Owner

Inventor Name Address # of Patent/Pub
McElvain Kenneth S
Los Altos, CA
105
Pierrat Christophe
Santa Clara, CA
84
Moroz Victor
Saratoga, CA
81
King Tsu-Jae
Fremont, CA
59
Pramanik Dipankar
Saratoga, CA
53
Pierrat Christophe
Not Provided
47
Diorio Christopher J
Shoreline, WA
44
Chiang Charles C
San Jose, CA
41
Kapur Rohit
Cupertino, CA
38
Lin Xi-Wei
Fremont, CA
37