TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Patent Owner
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- 202 8,065 total patents issued
- 7,126 Total Apps Published
- Jun 13, 2013 most recent publication
Details
- 8,065 Issued Patents
- 1,739 Issued in last 3 years
- 2,523 Published in last 3 years
- 77,050 Total Citation Count
- Nov 14, 1985 Earliest Filing
- 132 Expired/Abandoned/Withdrawn Patents
Technologies
Intl Class
Technology
# of Patents
Rank
Top Patents (by citation)
Patent #
Title
Filing Date
Issue Date
Intl Class
Cited #
5,568,629
Method for partitioning disk drives within a physical disk array and selectively assigning disk drive partitions into a logical disk array
Nov 04, 93
Oct 22, 96
[G06F]
214
6,143,604
Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)
Jun 04, 99
Nov 07, 00
[H01L]
193
5,943,581
Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits
Nov 05, 97
Aug 24, 99
[H01L]
177
5,575,706
Chemical/mechanical planarization (CMP) apparatus and polish method
Jan 11, 96
Nov 19, 96
[B24B]
171
Recent Publications
Publication #
Title
Filing Date
Pub Date
Intl Class
2013/0146,224
ADAPATIVE ENDPOINT METHOD FOR PAD LIFE EFFECT ON CHEMICAL MECHANICAL POLISHING
Feb 04, 13
Jun 13, 13
[H01L]
2013/0146,647
Integrated Reflow and Cleaning Process and Apparatus for Performing the Same
Dec 07, 11
Jun 13, 13
[B23K]
2013/0146,780
SYSTEMS AND METHODS PROVIDING ELECTRON BEAM WRITING TO A MEDIUM
Feb 01, 13
Jun 13, 13
[H01J]
2013/0146,893
SIC CRYSTALLINE ON SI SUBSTRATES TO ALLOW INTEGRATION OF GAN AND SI ELECTRONICS
Feb 06, 13
Jun 13, 13
[H01L]
2013/0146,949
MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE
Dec 13, 11
Jun 13, 13
[H01L]
2013/0146,981
ANTENNA CELL DESIGN TO PREVENT PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS
Dec 12, 11
Jun 13, 13
[H01L]
2013/0146,987
Integrated Semiconductor Structure for SRAM and Fabrication Methods Thereof
Dec 10, 12
Jun 13, 13
[H01L]
2013/0146,993
SEMICONDUCTOR STRUCTURE HAVING A POLYSILICON STRUCTURE AND METHOD OF FORMING SAME
Dec 08, 11
Jun 13, 13
[H01L]
2013/0147,031
SEMICONDUCTOR DEVICE WITH BUMP STRUCTURE ON POST-PASSIVATION INTERCONNCET
Dec 07, 11
Jun 13, 13
[H01L]
2013/0147,046
Integrated Technology for Partial Air Gap Low K Deposition
Dec 07, 11
Jun 13, 13
[H01L]
2013/0147,049
Circuit Probing Structures and Methods for Probing the Same
Dec 07, 11
Jun 13, 13
[H01L]
2013/0147,057
THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT
Dec 13, 11
Jun 13, 13
[H01L]
2013/0147,993
Apparatus and Method for Reducing Optical Cross-Talk in Image Sensors
Dec 03, 12
Jun 13, 13
[H04N]
2013/0149,871
CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL
Dec 07, 11
Jun 13, 13
[C23C, H01L]
2013/0140,578
CIRCUIT STRUCTURE HAVING ISLANDS BETWEEN SOURCE AND DRAIN
Dec 01, 11
Jun 06, 13
[H01L]
2013/0140,637
Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same
Feb 01, 13
Jun 06, 13
[H01L]
2013/0140,666
SELF-ALIGNED IMPLANTS TO REDUCE CROSS-TALK OF IMAGING SENSORS
Jan 08, 13
Jun 06, 13
[H01L]
2013/0140,715
Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same
Dec 28, 12
Jun 06, 13
[H01L]
2013/0141,962
Methods and Apparatus for finFET SRAM Arrays in Integrated Circuits
Dec 06, 11
Jun 06, 13
[G11C]
2013/0142,594
Methods for Transporting Wafers Between Wafer Holders and Chambers
Dec 01, 11
Jun 06, 13
[H01L]
2013/0143,361
Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices
Dec 01, 11
Jun 06, 13
[H01L]
2013/0143,391
REACTED LAYER FOR IMPROVING THICKNESS UNIFORMITY OF STRAINED STRUCTURES
Dec 01, 11
Jun 06, 13
[H01L]
2013/0144,419
INTEGRATED CIRCUIT MANUFACTURING TOOL CONDITION MONITORING SYSTEM AND METHOD
Dec 01, 11
Jun 06, 13
[G06F]
2013/0144,423
SYSTEMS AND METHODS OF AUTOMATIC BOUNDARY CONTROL FOR SEMICONDUCTOR PROCESSES
Dec 06, 11
Jun 06, 13
[G06F]
2013/0134,435
HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE
Oct 12, 12
May 30, 13
[H01L]
2013/0134,481
Split-Channel Transistor and Methods for Forming the Same
Nov 30, 11
May 30, 13
[H01L]
2013/0134,482
SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE
Oct 12, 12
May 30, 13
[H01L]
2013/0134,541
Metal Shielding Layer in Backside Illumination Image Sensor Chips and Methods for Forming the Same
Mar 14, 12
May 30, 13
[H01L]
2013/0134,542
DARK CURRENT REDUCTION FOR BACK SIDE ILLUMINATED IMAGE SENSOR
Nov 28, 11
May 30, 13
[H01L]
2013/0134,543
CMOS Image Sensor Big Via Bonding Pad Application for AICu Process
Dec 27, 12
May 30, 13
[H01L]
2013/0134,553
INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES
Jan 30, 12
May 30, 13
[H01L]
2013/0134,559
Chip-on-Wafer Structures and Methods for Forming the Same
Feb 15, 12
May 30, 13
[H01L]
2013/0136,149
TEMPERATURE SENSOR WITH DIGITAL TRIM AND TRIMMING METHOD THEREOF
Oct 25, 12
May 30, 13
[G01K]
2013/0136,873
APPARATUS AND METHOD WITH DEPOSITION CHAMBER HAVING MULTIPLE TARGETS AND MAGNETS
Nov 30, 11
May 30, 13
[C23C, B05C]
2013/0137,034
METHOD OF PRE-TREATING A WAFER SURFACE BEFORE APPLYING A SOLVENT-CONTAINING MATERIAL THEREON
Feb 03, 12
May 30, 13
[B08B, G03F]
2013/0137,236
Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling
Jan 14, 13
May 30, 13
[H01L]
2013/0137,238
METHOD FOR FORMING HIGH MOBILITY CHANNELS IN III-V FAMILY CHANNEL DEVICES
Feb 28, 12
May 30, 13
[H01L]
2013/0137,251
Uniform Shallow Trench Isolation Regions and the Method of Forming the Same
Nov 30, 11
May 30, 13
[H01L]
2013/0137,261
METHOD OF MODIFYING A LOW K DIELECTRIC LAYER HAVING ETCHED FEATURES AND THE RESULTING PRODUCT
Nov 29, 11
May 30, 13
[H01L]
2013/0137,266
MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES
Nov 29, 11
May 30, 13
[H01L]
2013/0139,120
COMPUTER IMPLEMENTED SYSTEM AND METHOD FOR LEAKAGE CALCULATION
Feb 23, 12
May 30, 13
[G06F]
2013/0139,121
RC Extraction Methodology for Floating Silicon Substrate with TSV
Feb 06, 12
May 30, 13
[G06F]
2013/0126,946
III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate
Jan 14, 13
May 23, 13
[H01L]
2013/0126,951
Method of Fabricating FinFET Device and Structure Thereof
Jan 18, 13
May 23, 13
[H01L]
2013/0126,953
Methods and Apparatus for MOS Capacitors in Replacement Gate Process
Nov 22, 11
May 23, 13
[H01L]
2013/0126,955
Methods and Apparatus for Hybrid MOS Capacitors in Replacement Gate Process
Nov 22, 11
May 23, 13
[H01L]
2013/0126,979
INTEGRATED CIRCUITS WITH ELECTRICAL FUSES AND METHODS OF FORMING THE SAME
Nov 22, 11
May 23, 13
[H01L]
2013/0126,985
(110) SURFACE ORIENTATION FOR REDUCING FERMI-LEVEL-PINNING BETWEEN HIGH-K DIELECTRIC AND GROUP III-V COMPOUND SEMICONDUCTOR SUBSTRATE
Nov 18, 11
May 23, 13
[H01L]
2013/0127,036
NOVEL MECHANISM FOR MEMS BUMP SIDE WALL ANGLE IMPROVEMENT
Nov 23, 11
May 23, 13
[H01L]
2013/0127,059
Adjusting Sizes of Connectors of Package Components
Nov 17, 11
May 23, 13
[G06F, H01L]
2013/0127,441
APPARATUS AND METHOD FOR ON-CHIP SAMPLING OF DYNAMIC IR VOLTAGE DROP
Nov 18, 11
May 23, 13
[G01R]
2013/0128,486
Forming Low Stress Joints Using Thermal Compress Bonding
Dec 28, 12
May 23, 13
[B23K, H05K]
2013/0128,655
METHOD AND APPARATUS FOR DUAL RAIL SRAM LEVEL SHIFTER WITH LATCHING
Nov 23, 11
May 23, 13
[G11C, H03L]
2013/0130,410
METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING
Jan 16, 13
May 23, 13
[H01L]
2013/0130,451
Semiconductor Device with Reliable High-Voltage Gate Oxide and Method of Manufacture Thereof
Dec 21, 12
May 23, 13
[H01L]
2013/0130,488
Method of Patterning a Metal Gate of Semiconductor Device
Jan 18, 13
May 23, 13
[H01L]
Recent Patents
Patent #
Title
Filing Date
Issue Date
Intl Class
8,461,045
Bond pad connection to redistribution lines having tapered profiles
Mar 17, 11
Jun 11, 13
[H01L]
8,462,510
Board-level package with tuned mass damping structure
May 11, 11
Jun 11, 13
[H01R, H01L, H05K, F16F]
8,463,419
System and method for improved automated semiconductor wafer manufacturing
Nov 12, 09
Jun 11, 13
[G06F]
8,464,186
Providing electron beam proximity effect correction by simulating write operations of polygonal shapes
Jan 21, 11
Jun 11, 13
[G06F]
8,455,357
Method of plating through wafer vias in a wafer for 3D packaging
Sep 28, 09
Jun 04, 13
[H01L]
8,455,971
Apparatus and method for improving charge transfer in backside illuminated image sensor
Feb 14, 11
Jun 04, 13
[H01L]
8,456,009
Semiconductor structure having an air-gap region and a method of manufacturing the same
Feb 18, 10
Jun 04, 13
[H01L]
8,456,207
Lock detector and method of detecting lock status for phase lock loop
Nov 16, 11
Jun 04, 13
[H03L]
8,456,942
Regulators regulating charge pump and memory circuits thereof
Jun 27, 12
Jun 04, 13
[G11C]
8,450,052
Double patterning strategy for contact hole and trench in photolithography
Oct 17, 11
May 28, 13
[G03F]
8,450,161
Method of fabricating a sealing structure for high-k metal gate
May 07, 12
May 28, 13
[H01L]
8,450,722
Magnetoresistive random access memory and method of making the same
Jul 15, 11
May 28, 13
[H01L]
8,450,834
Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers
Feb 16, 10
May 28, 13
[H01L]
8,451,671
Multiplexing circuit for high-speed, low leakage, column-multiplexing memory devices
Oct 15, 10
May 28, 13
[G11C]
8,452,439
Device performance parmeter tuning method and system
Mar 15, 11
May 28, 13
[G21C, G06F, G01N]
8,445,296
Apparatus and methods for end point determination in reactive ion etching
Jul 22, 11
May 21, 13
[H01L]
8,445,940
Source and drain feature profile for improving device performance
Jul 09, 12
May 21, 13
[H01L]
8,446,161
Method of self monitoring and self repair for a semiconductor IC
Nov 24, 09
May 21, 13
[G01R]
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