UNITED MEMORIES, INC.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
G11C STATIC STORES 7144
 
  
 
H03K PULSE TECHNIQUE 6125
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 1361

Top Patents (by citation)

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Recent Publications

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9350338 Linear progression delay registerSep 03, 14May 24, 16[H03K]
9252759 Linear progression delay registerSep 03, 14Feb 02, 16[H03K]
9246475 Dual-complementary integrating duty cycle detector with dead band noise rejectionApr 09, 14Jan 26, 16[H03K]
6568642 Angle bracketJun 16, 00May 27, 03[E16L]
6392304 Multi-chip memory apparatus and associated methodNov 12, 98May 21, 02[H01L]
6275432 Method of reading and writing data using local data read and local data write circuitsJul 17, 96Aug 14, 01[G11C]
6249469 Sense amplifier with local sense drivers and local read amplifiersJul 01, 96Jun 19, 01[G11C]
6208574 Sense amplifier with local column read amplifier and local data write driversMay 02, 95Mar 27, 01[G11C]
6201413 Synchronous integrated circuit device utilizing an integrated clock/command techniqueOct 01, 98Mar 13, 01[H03K]
6195302 Dual slope sense clock generatorJan 27, 00Feb 27, 01[G11C]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
2009/0073,786 EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND THOSE INCORPORATING EMBEDDED DRAMAbandonedSep 14, 07Mar 19, 09[G11C]
2007/0103,124 System and method for controlling the drive strength of output drivers in integrated circuit devicesAbandonedNov 04, 05May 10, 07[H02J, G05F]
2007/0096,787 Method for improving the timing resolution of DLL controlled delay linesAbandonedNov 03, 05May 03, 07[H03H]
2006/0229,839 Temperature sensing and monitoring technique for integrated circuit devicesAbandonedMar 29, 05Oct 12, 06[G01K]
2006/0190,678 Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tagAbandonedFeb 22, 05Aug 24, 06[G06F]
2006/0005,053 Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devicesAbandonedJun 30, 04Jan 05, 06[G06F]
2005/0289,293 Dual-port DRAM cell with simultaneous accessAbandonedJun 28, 04Dec 29, 05[G06F]
2005/0052,219 Integrated circuit transistor body bias regulation circuit and method for low voltage applicationsAbandonedAug 16, 04Mar 10, 05[G05F]

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