XILINX, INC.

Patent Owner

Follow Compare

Stats

Details

Technologies

Intl Class Technology # of Patents Rank
 
 
G06F ELECTRIC DIGITAL DATA PROCESSING 1253 24
 
 
H03K PULSE TECHNIQUE 700 2
 
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 252 11
 
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 228 102
 
 
G11C STATIC STORES 216 33
 
 
H04L TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION 116 72
 
 
H03L AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES 60 21
 
 
H03M CODING, DECODING OR CODE CONVERSION, IN GENERAL 58 45
 
 
H04B TRANSMISSION 52 111
 
 
H03B GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS 40 18
  • No Owners to Display

Top Patents (by citation)

Patent # Title Filing Date Issue Date Intl Class Cited #
RE34363 Configurable electrical circuit having configurable logic elements and configurable interconnects Jun 24, 91 Aug 31, 93 [H03K] 546
5,426,378 Programmable logic device which stores more than one configuration and means for switching configurations Apr 20, 94 Jun 20, 95 [H03K] 390
5,914,616 FPGA repeatable interconnect structure with hierarchical interconnect lines Feb 26, 97 Jun 22, 99 [H03K] 342
5,469,003 Hierarchically connectable configurable cellular array Nov 05, 93 Nov 21, 95 [H03K] 314
5,349,250 Logic structure and circuit for fast carry Sep 02, 93 Sep 20, 94 [H03K] 264
5,646,545 Time multiplexed programmable logic device Aug 18, 95 Jul 08, 97 [H03K] 261
6,601,227 Method for making large-scale ASIC using pre-engineered long distance routing structure Jun 27, 01 Jul 29, 03 [G06F] 241
5,343,406 Distributed memory architecture for a configurable logic array and method for using distributed memory Jul 28, 89 Aug 30, 94 [G06F, H03K] 237
6,150,838 FPGA configurable logic block with multi-purpose logic/memory circuit Feb 25, 99 Nov 21, 00 [G06F] 227
5,365,125 Logic cell for field programmable gate array having optional internal feedback and optional cascade Jul 23, 92 Nov 15, 94 [H03K] 224
  • No Patents to Display

Recent Publications

Publication # Title Filing Date Pub Date Intl Class
2013/0148,450 CONTENTION-FREE MEMORY ARRANGEMENT Dec 07, 11 Jun 13, 13 [G11C]
2013/0151,911 REDUCTION IN DECODER LOOP ITERATIONS Dec 07, 11 Jun 13, 13 [G06F, H03M]
2013/0144,926 MINIMUM MEAN SQUARE ERROR PROCESSING Jan 28, 13 Jun 06, 13 [G06F]
2013/0138,712 MINIMUM MEAN SQUARE ERROR PROCESSING Jan 28, 13 May 30, 13 [G06F]
2013/0138,879 CIRCUIT FOR AND METHOD OF ENABLING THE TRANSFER OF DATA BY AN INTEGRATED CIRCUIT Nov 28, 11 May 30, 13 [G06F]
2013/0117,504 EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRATED CIRCUIT Nov 08, 11 May 09, 13 [G06F]
2013/0101,066 SYSTEMS AND METHODS FOR DIGITAL PROCESSING BASED ON ACTIVE SIGNAL CHANNELS OF A COMMUNICATION SYSTEM Oct 21, 11 Apr 25, 13 [H04L]
2013/0093,074 MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH HEAT SINK Oct 13, 11 Apr 18, 13 [H01L]
2013/0094,507 PARALLEL PROCESSING OF NETWORK PACKETS Oct 17, 11 Apr 18, 13 [H04L]
2013/0063,861 INTERDIGITATED CAPACITOR HAVING DIGITS OF VARYING WIDTH Sep 09, 11 Mar 14, 13 [H01G]

View all publication…

  • No Publications to Display

Recent Patents

Patent # Title Filing Date Issue Date Intl Class
8,463,835 Circuit for and method of providing a floating-point adder Sep 13, 07 Jun 11, 13 [G06F]
8,453,092 T-coil network design for improved bandwidth and electrostatic discharge immunity Apr 06, 12 May 28, 13 [H01F, G06F, H01L, H03K]
8,446,169 Impedance tuning for termination Aug 26, 11 May 21, 13 [H03B, H03K]
8,446,195 Strobe signal management to clock data into a system Jun 04, 10 May 21, 13 [H03L]
8,447,581 Generating simulation code from a specification of a circuit design Sep 15, 09 May 21, 13 [G06F]
8,447,957 Coprocessor interface architecture and methods of operating the same Nov 14, 06 May 21, 13 [G06F]
8,448,122 Implementing sub-circuits with predictable behavior within a circuit design Apr 01, 09 May 21, 13 [G06F]
8,441,038 Nano relay with floating bridge Jan 20, 11 May 14, 13 [H01L]
8,441,562 Color filter array alignment detection Sep 02, 10 May 14, 13 [H04N]
8,442,105 Equalization for minimum mean-square-error successive-interference-cancellation Nov 02, 11 May 14, 13 [H03H, H03K]

View all Patent…

  • No Patents to Display

Top Inventors for This Owner

Inventor Name Address Patent #
Trimberger Stephen M
San Jose, US
209
Young Steven P
Boulder, US
196
New Bernard J
Carmel Valley, US
113
Lesea Austin H
Los Gatos, US
69
Bauer Trevor J
Boulder, US
66
Goetting F Erich
Cupertino, US
58
Wong Jennifer
Fremont, US
58
Rahman Arifur
San Jose, US
55
Schultz David P
San Jose, US
53
Milne Roger B
Boulder, US
49
  • No Inventor to Display