Sarah H Knickerbocker
Inventor
Stats
- 24 total patents issued
- 36 total patents filed
- most recent filing
This is official USPTO record data
Details
- 24 Issued Patents
- 36 Filed Patents
- 233 Total Citation Count
- Apr 23, 2012 Most Recent Filing
- Jul 18, 1988 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| INTERNATIONAL BUSINESS MACHINES CORPORATION | 1 3 5 2 1 1 1 1 1 2 1 2 1 1 1 1 | 1988 1990 1991 1992 1995 1999 2002 2003 2004 2005 2006 2007 2008 2009 2011 2012 |
| ULTRATECH, INC. | 2 | 2007 |
| INVENSAS CORPORATION | 1 1 4 2 | 2003 2004 2005 2009 |
Inventor Addresses
| Address | Duration |
|---|---|
| Hopewell Junction, NY | Nov 20, 90 - Jun 19, 08 |
| Hopewell Junction, NY, US | Jan 06, 09 - Aug 16, 12 |
Technology Profile
| Technology | # of Patents | |
|---|---|---|
| B05D: | PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MATERIALS TO SURFACES, IN GENERAL | 2 |
| B22F: | WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER | 2 |
| B23K: | SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM | 2 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 2012/0207,920 | 2012 | PROTECTING A MOLD HAVING A SUBSTANTIALLY PLANAR SURFACE PROVIDED WITH A PLURALITY OF MOLD CAVITIES | 0 |
| 2012/0193,014 | 2012 | REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING | 0 |
| 7,999,377 | 2011 | Method and structure for optimizing yield of 3-D chip manufacture | 0 |
| 2011/0079,702 | 2011 | FORMING A PROTECTIVE LAYER ON A MOLD AND MOLD HAVING A PROTECTIVE LAYER | 0 |
| 7,833,897 | 2010 | Process for making interconnect solder Pb-free bumps free from organo-tin/tin deposits on the wafer surface | 0 |
