Andy L Lee
Inventor
Stats
- 106 total patents issued
- 127 total patents filed
- most recent filing
This is official USPTO record data
Details
- 106 Issued Patents
- 127 Filed Patents
- 1238 Total Citation Count
- May 10, 2012 Most Recent Filing
- May 13, 1997 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| BROOKE, LAWRENCE L. | 1 | 2004 |
| ALTERA CORPORATION | 2 6 4 8 8 12 8 8 9 9 11 6 14 6 8 1 | 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 |
Inventor Addresses
| Address | Duration |
|---|---|
| 1227 Briarleaf Cir., San Jose, CA 95131 | Jan 01, 02 - Jan 01, 02 |
| San Jose, CA | Nov 02, 99 - Dec 02, 08 |
| San Jose, CA, US | Mar 17, 09 - Mar 26, 13 |
Technology Profile
| Technology | # of Patents | |
|---|---|---|
| C01D: | COMPOUNDS OF ALKALI METALS, i.e. LITHIUM, SODIUM, POTASSIUM, RUBIDIUM, CAESIUM, OR FRANCIUM | 1 |
| G01C: | MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY | 1 |
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 7 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| 8,407,649 | 2013 | PLD architecture for flexible placement of IP function blocks | 0 |
| 2013/0043,902 | 2013 | APPARATUS FOR IMPROVING PERFORMANCE OF FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED METHODS | 0 |
| 8,369,175 | 2013 | Memory elements with voltage overstress protection | 0 |
| 8,369,175 | 2013 | Memory elements with voltage overstress protection | 0 |
| 8,305,121 | 2012 | High-performance memory interface circuit architecture | 0 |
