Kevin A Norman
Inventor
Stats
- 31 total patents issued
- 31 total patents filed
- most recent filing
This is official USPTO record data
Details
- 31 Issued Patents
- 31 Filed Patents
- 1038 Total Citation Count
- Jun 5, 2003 Most Recent Filing
- Mar 6, 1987 Earliest Filing
Work History
| Patent Owner | Applications Filed | Year |
|---|---|---|
| CADENCE DESIGN SYSTEMS, INC. | 1 5 5 1 1 | 1995 1997 1999 2000 2001 |
| ALTERA CORPORATION | 1 2 1 3 1 2 1 3 5 2 6 1 1 2 | 1987 1988 1990 1991 1992 1993 1995 1996 1997 1998 1999 2000 2001 2003 |
| QUICKTURN DESIGN | 1 | 1999 |
| QUICKTURN DESIGN SYSTEMS, INC. | 1 1 | 1998 2003 |
Inventor Addresses
| Address | Duration |
|---|---|
| 2609 Hastings Dr., Belmont, CA 94002 | Jun 11, 96 - Jun 11, 96 |
| Belmont, CA | May 16, 89 - Apr 19, 05 |
| Belmont, CA, US | Sep 01, 09 - Sep 01, 09 |
| San Mateo, CA | Oct 25, 94 - Oct 25, 94 |
Technology Profile
| Technology | # of Patents | |
|---|---|---|
| G01B: | MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS | 1 |
| G01R: | MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES | 2 |
| G05F: | SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES | 1 |
Patents / Publication
| Patents / Publication # | Year of Publication / Issued | Title | Citations |
|---|---|---|---|
| RE40894 | 2009 | Sample and load scheme for observability internal nodes in a PLD | 0 |
| 6,882,176 | 2005 | High-performance programmable logic architecture | 3 |
| 6,570,404 | 2003 | High-performance programmable logic architecture | 10 |
| 6,353,552 | 2002 | PLD with on-chip memory having a shadow register | 29 |
| 6,317,367 | 2001 | FPGA with on-chip multiport memory | 13 |
