System, apparatus and method for segmenting a memory array

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United States of America Patent

PATENT NO 10062429
SERIAL NO

15488681

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Abstract

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In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Appu, Abhisek R El Dorado Hills, US 3 14
Borole, Bhushan Rancho Cordova, US 9 25
Koker, Altug El Dorado Hills, US 565 3602
Nekkanti, Sunil Rancho Cordova, US 6 29
Rajwani, Iqbal R Roseville, US 13 75
Thaploo, Anupama A Folsom, US 20 50

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