Accessing error statistics from DRAM memories having integrated error correction

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United States of America

PATENT NO 10572344
APP PUB NO 20180314590A1
SERIAL NO

15961010

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Abstract

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In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

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Patent Owner(s)

  • AGILENT TECHNOLOGIES TEXAS INSTRUMENTS INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kothamasu, Siva Srinivas Gunter, IN 12 26

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