Test structure and manufacturing method therefor

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 10600700
APP PUB NO 20190074232A1
SERIAL NO

15995301

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Abstract

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This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.

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Patent Owner(s)

Patent OwnerAddress
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION18 ZHANGJIANG ROAD PUDONG NEW AREA SHANGHAI 201203
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONNO 18 WEN CHANG RD ECONOMIC-TECHNOLOGICAL DEVELOPMENT AREA DAXING DISTRICT BEIJING 100716

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, GuangNing Shanghai, CN 1 0
Mao, YiPing Shanghai, CN 2 1

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