Memory controller error checking process using internal memory device codes

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 10606690
APP PUB NO 20190102246A1
SERIAL NO

15721252

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Abstract

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An apparatus is described. The apparatus includes a memory controller to receive data from a memory device. The memory controller includes error checking logic circuitry. The error checking logic circuitry is to receive an error checking code from the memory device. The error checking code is generated within the memory device from the data. The error checking logic circuitry includes circuitry to generate a second version of the error checking code from the data that was received from the memory device and compare the received error checking code with the second version of the error checking code to understand if the data that was received from the memory controller is corrupted.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Criss, Kjersten E Beaverton, US 10 108

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