Memory device and control method thereof
Number of patents in Portfolio can not be more than 2000
United States of America
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Mar 31, 2020
Grant Date -
N/A
app pub date -
Feb 13, 2019
filing date -
Feb 13, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device and a control method thereof are provided. The memory device includes I memory blocks, I global power lines and I first local driver modules. Each memory block includes M gate control lines and a plurality of transistor units arranged in M rows. Gates of the transistor units in the m-th row are electrically connected to the m-th gate control line. The I global power lines are electrically connected to I pre-driver circuits and the I memory blocks, respectively. Each first local driver module is electrically connected to one global power line and one memory block. Each first local driver module includes M first local driver circuits. The m-th first local driver circuit is electrically connected to the m-th gate control line.
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