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United States of America Patent

PATENT NO 10746568
APP PUB NO 20180216962A1
SERIAL NO

15856196

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Abstract

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Data output from each of the “n” delay elements and a remainder value output from a divider in the previous calculation are input to an adder, and an addition process for obtaining a total sum thereof is executed. In addition, a division process is performed by dividing the total sum output from the adder by “n,” and a quotient and a remainder are output from the divider. The remainder is delayed by a remainder delay element by one clock, is output to the adder, and is added in the next calculation.

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Patent Owner(s)

Patent OwnerAddress
SHIMADZU CORPORATION1 NISHINOKYO-KUWABARA-CHO NAKAGYO-KU KYOTO-SHI KYOTO 604-8511

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tsuji, Hiroshi Kyoto, JP 129 1979

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