Counter readout circuit
Number of patents in Portfolio can not be more than 2000
United States of America
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Dec 14, 2021
Grant Date -
May 28, 2020
app pub date -
Nov 21, 2019
filing date -
Nov 21, 2019
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.
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