Managing a mode to access a memory component or a logic component for machine learning computation in a memory sub-system

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United States of America Patent

PATENT NO 11720268
APP PUB NO 20220365693A1
SERIAL NO

17879597

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Abstract

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A system can include a memory device with an array of memory cells and a machine learning operation component. The machine learning operation component can perform a machine learning computation in association with the array of memory cells. The system can also include a processing device that is operatively coupled with the memory device to perform operations that include setting the memory device to a first mode based on a first mode setting signal received from a host system, where in the first mode, the processing device exposes the array of memory cells to the host system and routes input data from the host system to the array of memory cells. The operations can also include, setting the memory device to a second mode, where in the second mode, the processing device exposes the machine learning operation component to the host system.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC8000 SOUTH FEDERAL WAY BOISE ID 83716-9632

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kale, Poorna Folsom, US 246 1287

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