Synchronized parallel tile computation for large area lithography simulation

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United States of America Patent

PATENT NO 11747786
APP PUB NO 20220291659A1
SERIAL NO

17750828

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Abstract

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Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTDHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beylkin, Daniel San Jose, US 9 32
Ho, Kenneth Lik Kin Redwood City, US 10 15
Lei, Junjiang Fremont, US 29 153
Peng, Danping Fremont, US 41 662
Trivedi, Sagar Santa Clara, US 5 7
Xu, Fangbo San Jose, US 4 28

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