Oscillation system including frequency-locked loop logic circuit and operating method thereof
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United States of America Patent
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Apr 23, 2024
Grant Date -
Jan 12, 2023
app pub date -
Jul 8, 2022
filing date -
Jul 8, 2022
priority date (Note) -
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Abstract
A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.
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