Integrated circuit packages having stress-relieving features

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 12091310
APP PUB NO 20210371271A1
SERIAL NO

17331762

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods will result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.

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Patent Owner(s)

Patent OwnerAddress
APOGEE SEMICONDUCTOR INC840 E CENTRAL PKWY STE 140 PLANO TX 75074

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ghoshal, Abhijeet Plano, US 2 1
Grant, David A Edinburgh, GB 18 188

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