Readout circuit structure
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United States of America Patent
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Oct 15, 2024
Grant Date -
Jan 5, 2023
app pub date -
Jun 23, 2022
filing date -
Jul 2, 2021
priority date (Note) -
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status (Latency Note)
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Abstract
A readout circuit structure is provided, which includes: a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, here the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a first bit line, and is coupled to the other memory array by a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a second bit line, and is coupled to the other memory array by a second complementary bit line; a first equalization pipe, connected to the first bit line; a second equalization pipe, connected to the first complementary bit line; a third equalization pipe, connected to the second bit line; and a fourth equalization pipe, connected to the second complementary bit line.
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