Memory device having bitline segmented into bitline segments and related method for operating memory device
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United States of America
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Dec 24, 2024
Grant Date -
Jan 11, 2024
app pub date -
Sep 22, 2023
filing date -
Sep 22, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.
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