Memory device having row decoder array architecture

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12198753
APP PUB NO 20230147765A1
SERIAL NO

17953715

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Abstract

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A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG ELECTRONICS CO LTDGYEONGGI DO KOREA SUWON SUWON GYEONGGI-DO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jeon, Hongsoo Suwon-si, KR 22 22
Kim, Seungyeon Suwon-si, KR 28 74
Park, Jooyong Suwon-si, KR 24 27

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