Power efficient circuits and methods for phase alignment

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12212646
APP PUB NO 20230144225A1
SERIAL NO

17974970

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Abstract

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A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements. The timing-calibration circuit minimizes system-wide power consumption by limiting the number and usage of active phase interpolators for delay adjustment in favor of the passive fractional delay elements.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INC4453 NORTH FIRST STREET SUITE 100 SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kasibhatla, Pavan Kumar Bengaluru, IN 13 74
Mishra, Jitendra Bangalore, IN 2 0

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