Hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element for machine learning applications

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United States of America

PATENT NO 12242906
SERIAL NO

18927565

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A hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add processing element (PE) for machine learning (ML) applications is disclosed. The hardware-implemented hybrid analog-digital mixed-mode matrix multiply-add PE for ML applications involves using Fin Field-Effect Transistors (“FinFETs”), which provide excellent sub-threshold operation, thereby reducing power requirements, and use variation minimization strategies to improve the overall accuracy. In this way, hybrid analog-digital mixed-mode matrix multiply-add calculations are efficient, low power, and accurate, with the processing element itself in a relatively small surface area.

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Inventor Name Address # of filed Patents Total Citations
Konstadinidis, Georgios San Jose, US 14 108

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